mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 251

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC16Y3/916Y3
USER’S MANUAL
Delay after transfer can be used to provide a peripheral deselect interval. A delay can
also be inserted between consecutive transfers to allow serial A/D converters to com-
plete conversion. Writing a value to DTL[7:0] in SPCR1 specifies a delay period. The
DT bit in each command RAM byte determines whether the standard delay period (DT
= 0) or the user-specified delay period (DT = 1) is used. The following expression is
used to calculate the delay:
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/f
Adequate delay between transfers must be specified for long data streams because
the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices
need at least the standard delay between successive transfers. If the system clock is
operating at a slower rate, the delay between transfers must be increased proportion-
ately.
Freescale Semiconductor, Inc.
Delay after Transfer
Standard Delay after Transfer
For More Information On This Product,
Table 11-3 Bits Per Transfer
BITS[3:0]
QUEUED SERIAL MODULE
Go to: www.freescale.com
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits per Transfer
=
32 DTL[7:0]
----------------------------------- -
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
16
10
11
12
13
14
15
8
9
f
sys
=
-------- -
f
17
sys
if DT = 0
if DT = 1
sys
.
MOTOROLA
11-19