mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 412

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

WAIT[1:0] — Wait States
D.5.2 Flash EEPROM Test Register
FEE1TST — Flash EEPROM Test Register 1
FEE2TST — Flash EEPROM Test Register 2
FEE3TST — Flash EEPROM Test Register 3
D.5.3 Flash EEPROM Base Address Registers
D-34
FEE1BAH — Flash EEPROM Base Address Register High 1
FEE2BAH — Flash EEPROM Base Address Register High 2
FEE3BAH — Flash EEPROM Base Address Register High 3
FEE1BAL — Flash EEPROM Base Address Register Low 1
MOTOROLA
ADDR
SB
15
15
15
0
0
The state of WAIT[1:0] out of reset is determined by the value stored in the associated
shadow bits. WAIT[1:0] specifies the number of wait states inserted during accesses
to the flash EEPROM module. A wait state has the duration of one system clock cycle.
WAIT[1:0] affects both control block and array accesses, and can be written only if
LOCK = 0 and STOP = 1. Refer to Table D-25.
The value of WAIT[1:0] is compatible with the lower two bits of the DSACK field in the
SCIM chip-select option registers. An encoding of %11 in WAIT[1:0] corresponds to
an encoding for fast termination.
These registers are used for factory test only.
RESET:
RESET:
ADDR
SB
14
14
14
0
0
13
13
0
0
0
0
12
12
0
0
0
0
WAIT[1:0]
Freescale Semiconductor, Inc.
11
11
00
01
10
11
0
0
0
0
For More Information On This Product,
Table D-25 Wait State Encoding
10
10
0
0
0
0
Go to: www.freescale.com
9
0
0
9
0
0
Wait States
8
0
0
8
0
0
–1
0
1
2
ADDR
SB
23
7
7
0
0
ADDR
SB
22
6
6
0
0
Clocks Per Transfer
ADDR
SB
21
5
5
0
0
3
4
5
2
ADDR
SB
20
4
4
0
0
ADDR
SB
19
3
3
0
0
MC68HC16Y3/916Y3
ADDR
USER’S MANUAL
SB
18
2
2
0
0
$YFF802
$YFF822
$YFF842
$YFF804
$YFF824
$YFF844
ADDR
$YFF806
SB
17
1
1
0
0
ADDR
SB
16
0
0
0
0