mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 167

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.8.5 Interrupt Acknowledge Bus Cycles
MC68HC16Y3/916Y3
USER’S MANUAL
Interrupt acknowledge bus cycles are CPU space cycles that are generated during ex-
ception processing. For further information about the types of interrupt acknowledge
bus cycles determined by DSACK, refer to APPENDIX A ELECTRICAL CHARAC-
TERISTICS and the SCIM Reference Manual (SCIMRM/AD).
1. The CPU16 finishes higher priority exception processing or reaches an
2. Processor state is stacked, then the CCR PK extension field is cleared.
3. The interrupt acknowledge cycle begins:
4. Modules or external peripherals that have requested interrupt service decode
5. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-
6. The vector number is converted to a vector address.
7. The content of the vector address is loaded into the PC and the processor
a. FC[2:0] are driven to %111 (CPU space) encoding.
b. The address bus is driven as follows. ADDR[23:20] = %1111
c. Request priority is latched into the CCR IP field from the address bus.
a. When there is no contention (IARB = %0000), the spurious interrupt
b. The dominant interrupt source supplies a vector number and DSACK
c. The bus monitor asserts BERR and the CPU16 generates the spurious
d. The AVEC signal is asserted (the signal is asserted by the dominant
instruction boundary.
the priority value in ADDR[3:1]. If request priority is the same as acknowledged
priority, arbitration by IARB contention takes place.
lowing ways:
transfers control to the exception handler routine.
ADDR[19:16] = %1111, which indicates that the cycle is an interrupt
acknowledge CPU space cycle; ADDR[15:4] = %111111111111;
ADDR[3:1] = the priority of the interrupt request being acknowledged; and
ADDR0 = %1.
monitor asserts BERR, and the CPU16 generates the spurious interrupt
vector number.
signals appropriate to the access. The CPU16 acquires the vector
number.
interrupt vector number.
interrupt source), and the CPU16 generates an autovector number
corresponding to interrupt priority.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5-59