mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 216

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
10.7.5.1 Conversion Parameters
10.7.5.2 Conversion Modes
10-8
MOTOROLA
Single or multiple channel conversion
Table 10-5 describes the conversion parameters controlled by bits in ADCTL1.
Conversion modes are defined by the state of the SCAN, MULT, and S8CM bits in
ADCTL1. Table 10-6 shows mode numbering.
The following paragraphs describe each type of conversion mode:
Mode 0 — A single four-conversion sequence is performed on a single input channel
specified by the value in CD:CA. Each result is stored in a separate result register
(RSLT0 to RSLT3). The appropriate CCF bit in ADSTAT is set as each register is filled.
The SCF bit in ADSTAT is set when the conversion sequence is complete.
Mode 1 — A single eight-conversion sequence is performed on a single input channel
specified by the value in CD:CA. Each result is stored in a separate result register
(RSLT0 to RSLT7). The appropriate CCF bit in ADSTAT is set as each register is filled.
The SCF bit in ADSTAT is set when the conversion sequence is complete.
Single or continuous conversion
Conversion Parameter
Conversion channel
Length of sequence
Table 10-5 Conversion Parameters Controlled by ADCTL1
Freescale Semiconductor, Inc.
SCAN
For More Information On This Product,
Table 10-6 ADC Conversion Modes
0
0
0
0
1
1
1
1
ANALOG-TO-DIGITAL CONVERTER
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The value of the channel selection field (CD:CA) in ADCTL1 determines
which multiplexer inputs are used in a conversion sequence. There are
16 possible inputs. Seven inputs are external pins (AN[6:0]), and nine
are internal.
A conversion sequence consists of either four or eight conversions. The
number of conversions in a sequence is determined by the state of the
S8CM bit in ADCTL1.
Conversion can be limited to a single sequence or a sequence can be
performed continuously. The state of the SCAN bit in ADCTL1 deter-
mines whether single or continuous conversion is performed.
Conversion sequence(s) can be run on a single channel or on a block of
four or eight channels. Channel conversion is controlled by the state of
the MULT bit in ADCTL1.
MULT
0
0
1
1
0
0
1
1
S8CM
0
1
0
1
0
1
0
1
Description
Mode
0
1
2
3
4
5
6
7
MC68HC16Y3/916Y3
USER’S MANUAL

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