mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 403

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
D.3 Standby RAM Module
D.3.1 RAM Module Configuration Register
RAMMCR — RAM Module Configuration Register
STOP — Low-Power Stop Mode Enable
RLCK — RAM Base Address Lock
RASP[1:0] — RAM Array Space
MC68HC16Y3/916Y3
USER’S MANUAL
RESET:
STOP
15
1
Table D-18 shows the SRAM address map.
This bit controls whether SRAM operates normally or enters low-power stop mode. In
low-power stop mode, the array retains its contents, but cannot be read or written. This
bit can be read or written at any time.
RLCK defaults to zero on reset; it can be written once to a one, and may be read at
any time.
The RASP field limits access to the SRAM array in microcontrollers that support
separate user and supervisor operating modes. RASP1 has no effect because the
CPU16 operates in supervisor mode only. This bit may be read or written at any time.
Refer to Table D-19.
0 = SRAM operates normally.
1 = SRAM enters low-power stop mode.
0 = SRAM base address registers can be written.
1 = SRAM base address registers are locked and cannot be modified.
0
0
NOTES:
Address
$YFFB00
$YFFB02
$YFFB04
$YFFB06
1. Y = M111, where M is the logic state of the module mapping (MM) bit in the SCIMCR.
0
0
1
0
0
Table D-19 SRAM Array Address Space Type
Freescale Semiconductor, Inc.
RLCK
15
RASP[1:0]
11
For More Information On This Product,
0
Table D-18 SRAM Address Map
X0
X1
0
0
RAM Array Base Address Register High (RAMBAH)
RAM Array Base Address Register Low (RAMBAL)
RAM Module Configuration Register (RAMMCR)
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REGISTER SUMMARY
9
1
RASP[1:0]
RAM Test Register (RAMTST)
Program and data accesses
8
1
Program access only
Space
NOT USED
0
$YFFB00
MOTOROLA
D-25
0

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