mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 437

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

SPIF — QSPI Finished Flag
MODF — Mode Fault Flag
HALTA — Halt Acknowledge Flag
Bit 4 — Not Implemented
CPTQP[3:0] — Completed Queue Pointer
D.7.14 Receive Data RAM
RR[0:F] — Receive Data RAM
D.7.15 Transmit Data RAM
TR[0:F] — Transmit Data RAM
MC68HC16Y3/916Y3
USER’S MANUAL
When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state
from which it can later be restarted.
SPIF is set after execution of the command at the address in ENDQP[3:0].
The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the SS
input pin is negated by an external driver.
HALTA is set when the QSPI halts in response to setting the SPCR3 HALT bit.
CPTQP[3:0] points to the last command executed. It is updated when the current com-
mand is complete. When the first command in a queue is executing, CPTQP[3:0] con-
tains either the reset value $0 or a pointer to the last command completed in the
previous queue.
Data received by the QSPI is stored in this segment. The CPU16 reads this segment
to retrieve data from the QSPI. Data stored in receive RAM is right-justified. Unused
bits in a receive queue entry are set to zero by the QSPI upon completion of the
individual queue entry. Receive RAM data can be accessed using byte, word, or long-
word addressing.
Data that is to be transmitted by the QSPI is stored in this segment. The CPU16
normally writes one word of data into this segment for each queue command to be
executed. Information to be transmitted must be written to the transmit data RAM in a
right-justified format. The QSPI cannot modify information in the transmit data RAM.
The QSPI copies the information to its data serializer for transmission. Information
remains in the transmit RAM until overwritten.
0 = QSPI is not finished.
1 = QSPI is finished.
0 = Normal operation.
1 = Another SPI node requested to become the network SPI master while the QSPI
0 = QSPI is not halted.
1 = QSPI is halted.
was enabled in master mode.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
$YFFD00 – $YFFD1F
$YFFD20 – $YFFD3F
MOTOROLA
D-59