mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 134

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5-26
MOTOROLA
During a a bus transfer cycle, an external device signals its port size and indicates
completion of the bus cycle to the MCU through the use of the DSACK inputs, as
shown in Table 5-11. Chip-select logic can generate data size acknowledge signals
for an external device. Refer to 5.9 Chip-Selects for more information.
If the CPU is executing an instruction that reads a long-word operand from a 16-bit
port, the MCU latches the 16 bits of valid data and then runs another bus cycle to
obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read
cycles. The addressed device uses the DSACK signals to indicate the port width. For
instance, a 16-bit external device always returns DSACK for a 16-bit port (regardless
of whether the bus cycle is a byte or word operation).
Dynamic bus sizing requires that the portion of the data bus used for a transfer to or
from a particular port size be fixed. A 16-bit port must reside on data bus bits [15:0],
and an 8-bit port must reside on data bus bits [15:8]. This minimizes the number of bus
cycles needed to transfer data and ensures that the MCU transfers valid data.
The MCU always attempts to transfer the maximum amount of data on all bus cycles.
For a word operation, it is assumed that the port is 16 bits wide when the bus cycle
begins.
Operand bytes are designated as shown in Figure 5-10. OP[0:3] represent the order
of access. For instance, OP0 is the most significant byte of a long-word operand, and
is accessed first, while OP3, the least significant byte, is accessed last. The two bytes
of a word-length operand are OP0 (most significant) and OP1. The single byte of a
byte-length operand is OP0.
OPERAND
LONG WORD
THREE BYTE
WORD
BYTE
DSACK1
31
1
1
0
0
OP0
Freescale Semiconductor, Inc.
Table 5-11 Effect of DSACK Signals
For More Information On This Product,
Figure 5-10 Operand Byte Order
DSACK0
24
1
0
1
0
23
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OP1
OP0
Complete cycle — Data bus port size is 16 bits
Complete cycle — Data bus port size is 8 bits
BYTE ORDER
Insert wait states in current bus cycle
16 15
Reserved
OP2
OP1
OP0
Result
8 7
MC68HC16Y3/916Y3
OP3
OP2
OP1
OP0
USER’S MANUAL
OPERAND BYTE ORDER
0