mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 116

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5-8
MOTOROLA
The synthesizer locks when the VCO frequency is equal to f
by the filter time constant and by the amount of difference between the two comparator
inputs. Whenever a comparator input changes, the synthesizer must relock. Lock sta-
tus is shown by the SLOCK bit in SYNCR. During power-up, the MCU does not come
out of reset until the synthesizer locks. Crystal type, characteristic frequency, and lay-
out of external oscillator circuitry affect lock time.
When the clock synthesizer is used, SYNCR determines the system clock frequency
and certain operating parameters. The W and Y[5:0] bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. When the W or
Y values change, VCO frequency changes, and there is a VCO relock delay. The
SYNCR X bit controls a divide-by circuit that is not in the synthesizer feedback loop.
When X = 0 (reset state), a divide-by-four circuit is enabled, and the system clock fre-
quency is one-fourth the VCO frequency (f
enabled and system clock frequency is one-half the VCO frequency (f
relock delay when clock speed is changed by the X bit.
When a slow reference is used, one W bit and six Y bits are located in the PLL feed-
back path, enabling frequency multiplication by a factor of up to 256. The X bit is lo-
cated in the VCO clock output path to enable dividing the system clock frequency by
two without disturbing the PLL.
When using a slow reference, the clock frequency is determined by SYNCR bit set-
tings as follows:
The reset state of SYNCR ($3F00) results in a power-on f
is 32.768 kHz.
When a fast reference is used, three W bits are located in the PLL feedback path, en-
abling frequency multiplication by a factor from one to eight. Three Y bits and the X bit
are located in the VCO clock output path to provide the ability to slow the system clock
without disturbing the PLL.
When using a fast reference, the clock frequency is determined by SYNCR bit settings
as follows:
The reset state of SYNCR ($3F00) results in a power-on f
is 4.194 MHz.
Freescale Semiconductor, Inc.
For More Information On This Product,
f
sys
Go to: www.freescale.com
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). When X = 1, a divide-by-two circuit is
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of 8.388 MHz when f
of 8.388 MHz when f
. Lock time is affected
MC68HC16Y3/916Y3
VC0
USER’S MANUAL
). There is no
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