mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 266

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

12.2 MCCI Registers and Address Map
12.2.1 MCCI Global Registers
12.2.1.1 Low-Power Stop Mode
12-2
MOTOROLA
The SCI is a universal asynchronous receiver transmitter (UART) serial interface with
a standard non-return to zero (NRZ) mark/space format. It operates in either full- or
half-duplex mode: it contains separate transmitter- and receiver-enable bits and a dou-
ble transmit buffer. A modulus-type baud rate generator provides rates from 64 baud
to 524 kbaud with a 16.78-MHz system clock. Word length of either 8 or 9 bits is
software selectable. Optional parity generation and detection provide either even or
odd parity check capability. Advanced error detection circuitry catches glitches of up
to 1/16 of a bit time in duration. Wakeup functions allow the CPU to run uninterrupted
until meaningful data is received.
The MCCI address map occupies 64 bytes from address $YFFC00 to $YFFC3F. It
consists of MCCI global registers and SPI and SCI control, status, and data registers.
Writes to unimplemented register bits have no effect, and reads of unimplemented bits
always return zero.
The MM bit in the single-chip integration module 2 configuration register (SCIM2CR)
defines the most significant bit (ADDR23) of the IMB address for each module.
Because ADDR[23:20] are driven to the same bit as ADDR19, MM must be set to one.
If MM is cleared, IMB modules are inaccessible. Refer to 5.2.1 Module Mapping for
more information about how the state of MM affects the system.
The MCCI module configuration register (MMCR) contains bits and fields to place the
MCCI in low-power operation, establish the privilege level required to access MCCI
registers, and establish the priority of the MCCI during interrupt arbitration. The MCCI
test register (MTEST) is used only during factory test of the MCCI. The SCI interrupt
level register (ILSCI) determines the level of interrupts requested by each SCI. Sepa-
rate fields hold the interrupt-request levels for SCIA and SCIB. The MCCI interrupt
vector register (MIVR) determines which three vectors in the exception vector table
are to be used for MCCI interrupts. The SPI and both SCI interfaces have separate
interrupt vectors adjacent to one another. The SPI interrupt level register (ILSPI) de-
termines the priority level of interrupts requested by the SPI. The MCCI port data reg-
isters (PORTMC, PORTMCP) are used to configure port MCCI for general- purpose I/
O. The MCCI pin assignment register (MPAR) determines which of the SPI pins (with
the exception of SCK) are used by the SPI, and which pins are available for general-
purpose I/O. The MCCI data direction register (DDRM) configures each pins as an in-
put or output.
When the STOP bit in the MMCR is set, the IMB clock signal to most of the MCCI mod-
ule is disabled. This places the module in an idle state and minimizes power consump-
tion.
To ensure that the MCCI stops in a known state, assert the STOP bit before executing
the CPU LPSTOP instruction. Before asserting the STOP bit, disable the SPI (clear
MULTICHANNEL COMMUNICATION INTERFACE
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MC68HC16Y3/916Y3
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