mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 311

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

14.2.2 Timer Channels
14.2.3 Scheduler
14.2.4 Microengine
14.2.5 Host Interface
14.2.6 Parameter RAM
MC68HC16Y3/916Y3
USER’S MANUAL
The TPU2 has 16 independent channels, each connected to an MCU pin. The chan-
nels have identical hardware with the exception of channel 15, which has additional
output disable logic. Each channel consists of an event register and pin control logic.
The event register contains a 16-bit capture register, a 16-bit compare/match register,
and a 16-bit greater-than-or-equal-to comparator. The direction of each pin, either out-
put or input, is determined by the TPU microengine. Each channel can either use the
same time base for match and capture, or can use one time base for match and the
other for capture.
When a service request is received, the scheduler determines which TPU2 channel is
serviced by the microengine. A channel can request service for one of four reasons:
for host service, for a link to another channel, for a match event, or for a capture event.
The host system assigns each active channel one of three priorities: high, middle, or
low. When multiple service requests are received simultaneously, a priority-scheduling
mechanism grants service based on channel number and assigned priority.
The microengine is composed of a control store and an execution unit. Control-store
ROM holds the microcode for each factory-masked time function. When assigned to a
channel by the scheduler, the execution unit executes microcode for a function as-
signed to that channel by the CPU16. Microcode can also be executed from the TPU
flash EEPROM (TPUFLASH) module instead of the control store. The TPUFLASH
allows emulation and development of custom TPU microcode without the generation
of a microcode ROM mask. Refer to 14.3.6 Emulation Support for more information.
The host interface registers allow communication between the CPU16 and the TPU2,
both before and during execution of a time function. The registers are accessible from
the IMB through the TPU2 bus interface unit. Refer to 14.6 Host Interface Registers
and D.10 Time Processor Unit 2 (TPU2) for register bit/field definitions and address
mapping.
Parameter RAM occupies 256 bytes at the top of the system address map. Channel
parameters are organized as 128 16-bit words. Channels 0 through 15 each have
eight parameters. The parameter RAM address map in D.10.16 TPU2 Parameter
RAM shows how parameter words are organized in memory.
The CPU16 specifies function parameters by writing to the appropriate RAM address.
The TPU2 reads the RAM to determine channel operation. The TPU2 can also store
information to be read by the CPU16 in the parameter RAM. Detailed descriptions of
the parameters required by each time function are beyond the scope of this manual.
Refer to the TPU Reference Manual (TPURM/AD) and the Motorola TPU Literature
Package (TPULITPAK/D) for more information.
Freescale Semiconductor, Inc.
For More Information On This Product,
TIME PROCESSOR UNIT 2
Go to: www.freescale.com
MOTOROLA
14-3