mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 276

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

12.3.6 Wired-OR Open-Drain Outputs
12.3.7 Transfer Size and Direction
12.3.8 Write Collision
12.3.9 Mode Fault
12-12
MOTOROLA
Typically, SPI bus outputs are not open-drain unless multiple SPI masters are in the
system. If needed, the WOMP bit in SPCR can be set to provide wired-OR, open-drain
outputs. An external pull-up resistor should be used on each output line. WOMP
affects all SPI pins regardless of whether they are assigned to the SPI or used as
general-purpose I/O.
The SIZE bit in the SPCR selects a transfer size of 8 (SIZE = 0) or 16 (SIZE = 1) bits.
The LSBF bit in the SPCR determines whether serial shifting to and from the data
register begins with the LSB (LSBF = 1) or MSB (LSBF = 0).
A write collision occurs if an attempt is made to write the SPDR while a transfer is in
progress. Since the SPDR is not double buffered in the transmit direction, a successful
write to SPDR would cause data to be written directly into the SPI shift register.
Because this would corrupt any transfer in progress, a write collision error is generated
instead. The transfer continues undisturbed, the data that caused the error is not writ-
ten to the shifter, and the WCOL bit in SPSR is set. No SPI interrupt is generated.
A write collision is normally a slave error because a slave has no control over when a
master initiates a transfer. Since a master is in control of the transfer, software can
avoid a write collision error generated by the master. The SPI logic can, however,
detect a write collision in a master as well as in a slave.
What constitutes a transfer in progress depends on the SPI configuration. For a
master, a transfer starts when data is written to the SPDR and ends when SPIF is set.
For a slave, the beginning and ending points of a transfer depend on the value of
CPHA. When CPHA = 0, the transfer begins when SS is asserted and ends when it is
negated. When CPHA = 1, a transfer begins at the edge of the first SCK cycle and
ends when SPIF is set. Refer to 12.3.4 SPI Clock Phase and Polarity Controls for more
information on transfer periods and on avoiding write collision errors.
When a write collision occurs, the WCOL bit in the SPSR is set. To clear WCOL, read
the SPSR while WCOL is set, and then either read the SPDR (either before or after
SPIF is set) or write the SPDR after SPIF is set. (Writing the SPDR before SPIF is set
results in a second write collision error.) This process clears SPIF as well as WCOL.
When the SPI system is configured as a master and the SS input line is asserted, a
mode fault error occurs, and the MODF bit in the SPSR is set. Only an SPI master can
experience a mode fault error, caused when a second SPI device becomes a master
and selects this device as if it were a slave.
To avoid latchup caused by contention between two pin drivers, the MCU does the fol-
lowing when it detects a mode fault error:
MULTICHANNEL COMMUNICATION INTERFACE
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MC68HC16Y3/916Y3
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