mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 461

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
FOC[5:1] — Force Output Compare
FPWMA/B — Force PWM Value
PPROUT — PWM Clock Output Enable
PPR[2:0] — PWM Prescaler/PCLK Select
SFA — PWMA Slow/Fast Select
SFB — PWMB Slow/Fast Select
MC68HC16Y3/916Y3
USER’S MANUAL
FOC[5:1] correspond to OC[5:1].
This field selects one of seven prescaler taps or PCLK to be PWMCNT input. Refer to
Table D-52.
Table D–53 shows a range of PWM output frequencies using a 16.78 MHz system
clock.
0 = Has no effect.
1 = Causes pin action programmed for corresponding OC pin, but the OC flag is
0 = PWM pin A/B is used for PWM functions; normal operation.
1 = PWM pin A/B is used for discrete output. The value of the F1A/B bit will be driv-
0 = Normal PWM operation on PWMA.
1 = Clock selected by PPR[2:0] is driven out PWMA pin.
0 = PWMA period is 256 PWMCNT increments long.
1 = PWMA period is 32768 PWMCNT increments long.
0 = PWMB period is 256 PWMCNT increments long.
1 = PWMB period is 32768 PWMCNT increments long.
not set. FOC[5:1] correspond to OC[5:1].
en out on the PWMA/B pin. This is true for PWMA regardless of the state of the
PPROUT bit.
Freescale Semiconductor, Inc.
PPR[2:0]
For More Information On This Product,
000
001
010
011
100
101
110
111
Table D-52 PPR[2:0] Field
Go to: www.freescale.com
System Clock Divide-by Factor
PCLK
128
16
32
64
2
4
8
MOTOROLA
D-83

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