mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 123

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 21Ah
Label: interrupt2_enable
Reset Value: 0000h
miscreg_interrupt2_enable
rxtdmreg_interrupt2_enable
aal0alarm_interrupt2_enable
clkrecovalarm_interrupt2_enable
erroralarm_interrupt2_enable
reserved
Address: 220h
Label: txa_clk_gen
Reset Value: 0403h
txa_clk_div[5:0]
txa_clk_divisor_load_now
txa_clk_inv
txa_clk_src[2:0]
txa_clk_oe
Label
Label
Bit Position
Bit Position
Table 52 - Tx A Clock Division Register
Table 51 - Interrupt 2 Enable Register
15:12
10:8
5:0
10
11
11
7
8
9
6
7
Zarlink Semiconductor Inc.
Type
Type
RW
RW
RW
RW
RW
RW
PUL This bit, when written to '1', will force the new txa_clk_div
MT90502
RW
RW
RW
RW
123
When '1' and the corresponding active bit in reg 210h is
active, interrupt2 will be active.
When '1' and the corresponding active bit in reg 210h is
active, interrupt2 will be active.
When '1' and the corresponding active bit in reg 210h is
active, interrupt2 will be active.
When '1' and the corresponding active bit in reg 210h is
active, interrupt2 will be active.
When '1' and the corresponding active bit in reg 210h is
active, interrupt2 will be active.
Reserved. Must always be “0000”
txa_clk clock source division value. The txa_clk clock
source (selected using txa_clk_src) can be divided before
being sent out on UTOPIA. Note that odd values will force
the duty cycle to be maintained, rather than returning it to
50-50.
to be applied immediately (possibly causing glitches on
the txa_clk). This bit should only be set to one when
loading the divisor when the txa_clk_present bit is
cleared.
Note that it is possible to dynamically change the divisor
value without causing glitches on the output clock if this
bit is not written to 1.
When '1', the txa_clk's source will be inverted before
being driven out on the txa_clk pin.
“000” =txa_clk_in; “001” =txb_clk_in; ”010”=txc_clk_in;
“011”=rxa_clk_in; “100” =rxb_clk_in; “101”=rxc_clk_in;
“110”=mem_clk; others=reserved.
txa_clk output enable. Active high.
Description
Description
Data Sheet