mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 124

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 220h
Label: txa_clk_gen
Reset Value: 0403h
txa_clk_present
txa_clk_divisor_reset
reserved
Address: 222h
Label: txb_clk_gen
Reset Value: 0403h
txb_clk_div[5:0]
txb_clk_divisor_load_now
txb_clk_inv
txb_clk_src[2:0]
txb_clk_oe
txb_clk_present
txb_clk_divisor_reset
reserved
Label
Label
Bit Position
Bit Position
15:14
Table 53 - Tx B Clock Division Register
10:8
Table 52 - Tx A Clock Division Register
5:0
12
13
11
6
7
15:14
12
13
Zarlink Semiconductor Inc.
Type
PUL This bit, when written to '1', will force the new txb_clk_div to
RW txb_clk clock source division value. The txb_clk clock source
RW When '1', the txb_clk's source will be inverted before being
RW “000”=txa_clk_in; “001” =txb_clk_in; “010”=txc_clk_in;
RW txb_clk output enable. Active high.
RW Set to '1' when the txb_clk is present. If the user does not
RW When '0', will reset the clock division.
RW Reserved. Must always be “00”
Type
MT90502
RW
RW
RW
(selected using txb_clk_src) can be divided before being
sent out on UTOPIA. Note that odd values will force the duty
cycle to be maintained, rather than returning it to 50-50.
be applied immediately (possibly causing glitches on the
txb_clk). This bit should only be set to one when loading the
divisor when the txb_clk_present bit is cleared.
Note that it is possible to dynamically change the divisor
value without causing glitches on the output clock if this bit is
not written to 1.
driven out on the txb_clk pin.
“011”=rxa_clk_in; “100”=rxb_clk_in; “101”=rxc_clk_in;
“110”=mem_clk; others=reserved.
want to use the txa UTOPIA interface, this bit should be left
at '0' regardless of the presence of the txb_clk.
124
Set to '1' when the txa_clk is present. If the user does not
When '0', will reset the clock division.
Reserved. Must always be “00”
want to use the txa UTOPIA interface, this bit should be
left at '0' regardless of the presence of the txa_clk.
Description
Description
Data Sheet