mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 60

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

For HDLC CPS-Packets, the RX SAR performs zero-insertion and appends the HDLC header and CRC (as
necessary) to the packet before writing it to the circular buffer. The RX SAR can be configured to either bit-wise or
byte-wise zero-insertion (one method for all of the HDLC channels). It can also write packets either with or without
an AAL2 header.
2.4.4
The MT90502 is capable of calculating the elapsed time between the reception of two CPS-Packets. Based on the
time elapsed and the difference in the sequence number in the UUI of the received CPS-Packet and that of the
previous CPS-Packet, a count of how many CPS-Packets have been lost can be found. The circular buffer write
pointer is adjusted to take the number of CPS-Packets lost into account before beginning to write the received
bytes. This algorithm is only successful if the PDV between packets is smaller than a complete wrap of the UUI
sequence counter. An enable bit (LC) in the CPS-Packet disassembly structure allows the CPS-Packet loss
compensation to be turned on or off.
2.4.5
If the CID Description Structure denotes a CPS-Packet as a CPU CPS-Packet, the CPS-Packet will be written into
the CPU CPS-Packet FIFO in external memory and a CPU CPS-Packet report structure will be generated (see
Section 2.4.7, Errors and Events on page 61). The CPU is alerted to the presence of CPU CPS-Packets through
the CPU CPS-Packet report structures. The CPU CPS-Packet base address can be read from the CPS-Packet
report structure.
The size of the CPU CPS-Packet FIFO is programmable (register 440h) as is its base address (register 440h). The
size of the FIFO can vary from 16 KB to 128 KB. The CPU is responsible for updating the read pointer (register
442h) following each read.
CPS-Packet Loss Compensation
CPU CPS-Packets
V alid Voice Sam ples (nibble in uppe r bits):
b8
b8
b8
b8
b8
1
1
1
1
1
16 kbps
b7
b7
b7
b7
b7
SID Entrie s:
Write back by tes:
24 kbps
ADPCM 40kbps
32kbps
b6
b6
b6
b6
b6
b5
b5
b5
b5
b5
1
PCM Sample
b4
b4
b4
b4
b4
1
0
b3
b3
b3
b3
b3
1
0
0
Figure 26 - Format of RX Circular Buffer
b2
b2
b2
b2
b2
1
0
0
0
b1
b1
b1
b1
b1
0
0
0
0
Format of RX Circular Buffe r
b0
b0
b0
b0
b0
0
0
0
0
b8
b8
Zarlink Semiconductor Inc.
0
0
b7
b7
1
0
MT90502
b6
b6
0
Tone Buffer Number
60
b5
b5
0
b4
b4
0
b3
b3
0
b2
b2
0
V alid Voice Sam ples (nibble in lowe r bits):
b8
b8
b8
b8
b8
1
1
1
1
1
b1
b1
0
b7
b7
b7
b7
b7
0
0
0
0
b0
b0
0
b6
b6
b6
b6
b6
0
0
0
0
b5
b5
b5
b5
b5
0-127 = tones/silence/null
Write Back
1
0
0
0
PCM Sample
b4
b4
b4
b4
b4
1
0
0
ADPCM 40kbps
b3
b3
b3
b3
b3
1
0
pattern.
32kbps
b2
b2
b2
b2
b2
1
24 kbps
16 kbps
b1
b1
b1
b1
b1
rx9.cdd
b0
b0
b0
b0
b0
Data Sheet