mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 41

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mt90502ag2

Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
2.2.3.3
In addition to a zero, one, or two byte address, an HDLC packet may also contain a control byte and a two-byte
CRC. The 5 MSBs of the HDLC control byte can be used as the UUI in the AAL2 CPS-Packet formed from that
HDLC packet.
The TX TDM calculates the length of each HDLC packet and stores it in the Length field of the each TX TDM Write
Cache entry.
2.2.3.4
The data field of an HDLC packet can contain an AAL2 CPS-Packet with or without a header. This is configured for
all HDLC streams in register 500h. When the packaging_type field of register 500h is set to ‘1’, all HDLC packets
will carry complete CPS-Packets with both header and payload. They will be treated as “raw” AAL2 CPS-Packets.
For “raw” AAL2 CPS-Packets, the CID is ignored and replaced by the CID in the CPS-Packet final assembly
structure. The LI is ignored and re-calculated by the TX TDM module. The UUI is passed on as the UUI for the
AAL2 CPS-Packet. The HEC is ignored and regenerated based on the new CID/UUI/LI.
Fields in Italic are used by hardware only. Fields in Plain are written to by the CPU/Software.
Index of the base structure given by HDLC Stream Number in TX CAM.
structures located in internal TX TDM Control Memory (8000h to BFF0h).
Each structure is 16-bytes in size.
UUI: The 5 MSBs of the control byte of the HDLC CPS-Packet. These can be used as
Control Bytes and Length
“Raw” AAL2 CPS-Packets
+0h
+2h
+4h
+6h
+8h
+10h
+12h
+14h
+16h
+18h
+20h
+22h
+24h
+26h
+28h
the UUI value on AAL2. For all other fields, refer to the previous figure.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
HBC
HDLC Channel Number
CPSP Buf RP [7:0]
CPSP Buf WP [7:0]
CPSP Buf WP [7:0]
TX TDM Control Memory (AAL2 header present in HDLC data)
Count 1s
Figure 14 - HDLC CPS-Packet Assembly Structure
HDLC CPS-Packet Assembly Structure
History Bits & Valid [7:0[
Zarlink Semiconductor Inc.
CPSP Buf SOP [7:1]
Number of HDLC Channels
CPSP Buf RP [7:1]
CPSP Buf SOP [7:1]
CPSP Buf SOP [7:1]
CPSP Buf RP [7:1]
CPSP Buf RP [7:1]
UUI [4:0]
UUI [4:0]
UUI [4:0]
MT90502
V
V
V
41
Header Type
CRC
1
Third and up to N
successive HDLC Structures
on a HDLC Stream
Base HDLC Structure for
all HDLC Streams
Second HDLC Structure
Channels on a HDLC Stream
Reserved
Data Sheet

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