mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 18
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mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
(204 pages)
- Current page: 18 of 204
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AF2
AF11, AD10, AF10, AD9,
AF9, AE8, AC7, AE7,
AD7, AF8, AD8, AE9,
AC9, AE10, AC10, AE11
AD11, AF7
AF4, AE3
AE5
AE4, AF5
AE12
AD12
AF12
AD6, AE6, AF6, AD5,
AF3, AC12, AE13, AF13,
AF14, AD13, AE14,
AC14, AE15, AC15,
AE16, AF16, AD15,
AF15, AD14
AE22, AD22, AF24,
AE24, AD25, AC25,
AB24, AB26, AB25,
AC26, AD26, AE26,
AE23, AF23, AD21, AE21
AF22, AA24
W25, W26
Y25
W24, Y26
AC20
AD20
AF21
AA25, AA26, Y23, Y24,
AC21, AE20, AC19,
AF20, AE19, AD19,
AF19, AE18, AC17,
AE17, AD16, AF17,
AD17, AF18, AD18
Pin
Z
Z
1
Z
Z
Z
Z
Z
rst
Z
Z
Z
Z
Z
Z
Z
1
mem_clk
mema_d[15:0]
mema_p[1:0]
mema_cs[1:0]
mema_r/w
mema_bws[1:0]
mema_cas
mema_ras
mema_we
mema_a[18:0]
memb_d[15:0]
memb_p[1:0]
memb_cs[1:0]
memb_r/w
memb_bws[1:0]
memb_cas
memb_ras
memb_we
memb_a[18:0]
Name
Table 4 - Memory Interface Pins
Zarlink Semiconductor Inc.
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
MT90502
I
LVTTL
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
LVTTL 6 mA
18
Type
memory clock (common to both bank A and B). It
is also employed as the internal master clock.
SDRAM/SSRAM bank A data bus
SDRAM/SSRAM bank A parity bits
SSRAM bank A Chip selects 1, 0
SSRAM bank A Read/Write
SSRAM bank A Byte Write Selects 1:0
SDRAM bank A Column Address Select
SDRAM bank A Row Address Select
SDRAM bank A Write Enable
SDRAM/SSRAM bank A address bus
SDRAM/SSRAM bank B data bus
SDRAM/SSRAM bank B parity bits
SSRAM bank B Chip selects 1,0
SSRAM bank B Read/Write
SSRAM bank B Byte Write Selects 1,0
SDRAM bank B Column Address Select
SDRAM bank B Row Address Select
SDRAM bank B Write Enable
SDRAM/SSRAM bank B address bus
Description
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