mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 16

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

D3
C1
A2, D4, A1, B1, C2
A3, B3, B2
B4
J4
D2
G1
G2
E3, E2, E1, F3, F2, F1, G4, G3
D1
L1
H3
L2
L3
H1, J3, J2, J1, K4, K3, K2, K1
H2
Pins
rst
Table 2 - UTOPIA Interface Pins (continued)
Z
Z
Z
Z
Z
Z
Z
Z
1. rxb_enb
2. rxb_clav
1. rxb_clav
2. rxb_enb
1. rxb_d[4:0]
2. rxa_addr[4:0]
1. rxb_d[7:5]
2. txa_addr[2:0]
1. rxb_prty
2. txa_addr[3]
txc_clk
txc_soc
1. txc_enb
2. txc_clav
1. txc_clav
2. txc_enb
txc_d[7:0]
txc_prty
rxc_clk
rxc_soc
1. rxc_enb
2. rxc_clav
1. rxc_clav
2. rxc_enb
rxc_d[7:0]
rxc_prty
Name
Zarlink Semiconductor Inc.
MT90502
16
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
LVTTL 6 mA (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
Type
1. UTOPIA port B RX Enable in
ATM mode
2. UTOPIA port B RX Cell
Available in PHY mode
1. UTOPIA port B RX Cell
Available in ATM mode
2. UTOPIA port B RX Enable in
PHY mode
1. UTOPIA port B RX Data bus
[4:0]
2. rxa_addr[4:0] when port A and
B are combined
1. UTOPIA port B RX Data bus
[7:5]
2. txa_addr[2:0] when port A and
B are combined
1. UTOPIA port B RX Parity.
2. txa_addr[3] when port A and B
are combined.
UTOPIA port C TX Start of Cell
1. UTOPIA port C TX Enable in
ATM mode
2. UTOPIA port C TX Cell
Available in PHY mode
1. UTOPIA port C TX Cell
Available in ATM mode
2. UTOPIA port C TX Enable in
PHY mode
UTOPIA port C RX Start of Cell
1. UTOPIA port C RX Enable in
ATM mode
2. UTOPIA port C RX Cell
Available in PHY mode
Available in ATM mode
2. UTOPIA port C RX Enable in
PHY mode
UTOPIA port C RX Parity
UTOPIA port C TX clock
UTOPIA port C TX Data bus
UTOPIA port C TX Parity
UTOPIA port C RX clock
1. UTOPIA port C RX Cell
UTOPIA port C RX Data bus
Description
Data Sheet