mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 50

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

.
+FFCh
+FF8h
+000h
+004h
The number of structures in this table is
programmed with respect to the max. number of
channels:{128, 256, 512, 1023}.
Note: This structure is used by hardware only.
Cell Assembly Event Queue
(located in TX SSRAM)
Event 1023
Event 1022
Event 0
Event 1
TXD: The TX Destination field, as defined in the TX AAL2 VC Structure.
TX SAR Input FIFO structure is 64-bytes in size, located in internal memory at
2000h to 20C0h. The AAL0 Input FIFO structure is 64-bytes in size, located in
internal memory at 2100h to 21C0h.
+3Ah
+3Ch
+3Eh
+30h
+32h
+34h
+36h
+38h
+0h
+2h
+4h
+6h
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3
GFC/VPI
TXD
Payload Byte 44
Payload Byte 46
Payload Byte 0
Payload Byte 2
Cell Format of TX SAR Input FIFO
Figure 20 - Cell Assembly Event Queue
VCI [11:0]
Figure 21 - TX Cell Format
Zarlink Semiconductor Inc.
VC Number [9:0]: Number of the VC in which a cell must be assembled.
Num of Payload Bytes: Indicates the number of payload bytes that will be
packaged in the cell that will be assembled. Range 1 to 47.
The Cell Assembly Event Queue is located in TX SSRAM at addresses +2000h
to +21FCh, +4000h to +43FCh, +8000h to +87FCh and +10000h to +10FFCh
for 128, 256, 512 and 1023 channels respectively.
Each structure is 4-bytes in size.
+0h
+2h
VPI
MT90502
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3
50
Payload Byte 45
Payload Byte 47
Payload Byte 1
Payload Byte 3
VC Number[9:0]
Note: This structure used by hardware only.
VCI [15:12]
b2
PTI
VC Send Event
b1
b0
OAM
CLP
Num of Payload Bytes
Reserved
b2
Data Sheet
b1
b0