mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 134

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

3.4
Address: 304h
Label: status0_ie
Reset Value: 0000h
aal0_cell_fifo_empty_ie
reserved
Address: 310h
Label: aal0_monitor
Reset Value: 0000h
aal0_cell_write_ok
reserved
Address: 400h
Label: control
Reset Value: 0000h
hdlc_type
packaging_type
nibble_mode
reserved
test_status
RX Registers
Label
Label
Label
Bit Position
Bit Position
Bit Position
14:3
15:1
15
1
0
0
2
15:1
0
Table 71 - TX Interrupt Enable Register
Table 72 - TX AAL0 Monitor Register
Table 73 - RX Control Register
Type
RO
RO
Type
RW
RW
RW
RW
TS
Type
RO
IE
Zarlink Semiconductor Inc.
When '1', CPU can write another AAL0 cell to internal FIFO
Reserved. Always read as “0000_0000_0000_000”
‘0'=Bit wide HDLC Framing; '1'=Byte Wide HDLC Framing.
‘0' = no AAL2 Header in HDLC Data Field; '1' = Raw AAL2
CPS-Packet in HDLC Data Field
‘0' = High bits used for ADPCM nibble, '1' = low bits used for
ADPCM nibble
Reserved. Must Always be “0000_0000_0000”
Reserved. Must always be “0”.
When ‘1’ and the corresponding status bit is ‘1’ an interrupt will
be generated.
Reserved. Always read as “0000_0000_0000_000”
MT90502
134
Description
Description
Description
Data Sheet