mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 163

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

Address: 702h
Label: status0
Reset Value: 0000h
mem_clk_alarm0
mem_clk_alarm1
ct_frame_a_bad
ct_frame_b_bad
ct_c8_a_bad
ct_c8_b_bad
adapa_point_lost
adapb_point_lost
tx_time_slot_pnt_out_of_s
ync
Reserved
ct_frame_a_bad_rol
ct_frame_b_bad_rol
ct_c8_a_bad_rol
ct_c8_b_bad_rol
Label
Position
11:9
Bit
12
13
14
15
0
1
2
3
4
5
6
7
8
Table 161 - H.100/H.110 Status Register 0
Type
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
ROL
Alarm that can be used to generate a programmable interval interrupt
(me 9998888m_clk Alarm Timer 0). This bit is set when the
mem_clk_count[31:16] matches the mem_clk_alarm0_count. Write a 1
to clear the bit.
Alarm that can be used to generate a programmable interval interrupt
(mem_clk Alarm Timer 1). This bit is set when the
mem_clk_count[31:16] matches the mem_clk_alarm1_count. Write a 1
to clear the bit.
When the ct_frame_a is considered bad by the hardware, this bit is set.
The frame is considered bad if it is not low one cycle out of 1024. Write a
1 to clear the bit.
When the ct_frame_b is considered bad by the hardware, this bit is set.
The frame is considered bad if it is not low one cycle out of 1024. Write a
1 to clear the bit.
When the ct_c8_a is considered bad by the hardware, this bit is set. The
clock is considered bad if its rising edges are too close or too far
apart(i.e. if the rising edge does not arrive within 35 ns to the expected
position). Write a 1 to clear the bit.
When the ct_c8_b is considered bad by the hardware, this bit is set. The
clock is considered bad if its rising edges are too close or too far
apart(i.e. if the rising edge does not arrive within 35 ns to the expected
position). Write a 1 to clear the bit.
When a point is lost due to too much latency to the external memory, this
bit is set. This is not a fatal error, but an indication that this phenomenon
occurred. Point lost must be compensated for by software using the UUI
field in each point. Write a 1 to clear the bit.
When a point is lost due to too much latency to the external memory, this
bit is set. This is not a fatal error, but an indication that this phenomenon
occurred. Point lost must be compensated for by software using the UUI
field in each point. Write a 1 to clear the bit.
When this bit is high, the H.100 slave has lost its framing on the bus.
This bit will cause the H.100 data pins to be tri-stated. Note that this bit
will always be set at start-up. Write a 1 to clear the bit.
Reserved. Must always be “000”
Same as bit 2, except this bit has no effect on the slaveship state.
Same as bit 3, except this bit has no effect on the slaveship state.
Same as bit 4, except this bit has no effect on the slaveship state.
Same as bit 5, except this bit has no effect on the slaveship state.
Zarlink Semiconductor Inc.
MT90502
163
Description
Data Sheet