mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 45

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.2.4.2
+3FE000h
+3FF000h
CPSPDQ Table in SDRAM
+00000h
+01000h
The number of CPSPDQ in this
table can be programmed to {128,
256, 512, 1023}.
CPS-Packet Descriptor structures
are fixed and are located at the
beginning
(2000000h).
Each structure is 8-bytes in size.
Note: This structure is used by the
hardware only.
CPSPDQ - VC 1022
CPSPDQ - VC 1023
CPSPDQ - VC 0
CPSPDQ - VC 1
CPS-Packet Descriptor Queue
of
SDRAM
memory
CPS-Packet Descriptor Queue
+FF0h
+FF8h
+10h
+18h
+0h
+8h
CPSPBA: CPS-Packet Base Address [20:0]: Word pointer pointing to the beginning of a
CPS-Packet. Note that the CPS-Packet as such wraps at the boundary of its circular buffer.
Size: Indicates the “wrap” boundary of the CPS-Packet. “0000” = 256 bytes; “0001” = 256 x 2^
“0002” = 256 x 2^
CID: Channel ID that will be passed on in the AAL2 CPS-Packet.
Length: Length of the data part of the packet. Defined in the same way as the LI.
UUI: User to User indicator that will be passed on in the AAL2 CPS-Packet.
CPU: CPU Sourced CPS-Packet. “0” = CPS-Packet from TDM bus; “1” = CPS-Packet from CPU.
WB: When “1”, the TX RX SAR will NOT write back the CPSP Read Pointer in the TXTDM PCM
Control Structure.
(one per VC)
Figure 17 - CPS-Packet Descriptor Queue
Descriptor 510
Descriptor 511
Descriptor 0
Descriptor 1
Descriptor 2
Descriptor 3
Zarlink Semiconductor Inc.
2
; ... “1101” = 2M bytes.
MT90502
+6h
45
+0h
+2h
+4h CPSP
b15
CPSPBA [4:0]
b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Size
(one per pending CPS-Packet)
CPS-Packet Base Address [20:5]
CPS-Packet Descriptor
WB
Length [5:0]
Reserved
CID
Data Sheet
UUI
1
;