mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 145

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

3.6
Address: 600h
Label: control
Reset Value: 0000h
rxa_ena
rxb_ena
rxc_ena
porta_sar_mode
portb_sar_mode
portc_sar_mode
porta_level2_mode
txa_always_drive_dat_soc_par
txb_always_drive_dat_soc_par
txc_always_drive_dat_soc_par
clav_enb_oe
reserved
test_status
UTOPIA Registers
Label
Position
Table 102 - UTOPIA Control Register 1
14:11
Bit
10
15
0
1
2
3
4
5
6
7
8
9
Type
RW 0' = RXA Disabled; '1' = RXA Operates Normally.
RW 0' = RXB Disabled; '1' = RXB Operates Normally.
RW 0' = RXC Disabled; '1' = RXC Operates Normally.
RW Puts TXC/RXC in PHY or SAR mode. '1'=PHY Mode; '0'=SAR
RW 0' = only drive when selected; '1' = always drive
RW 0' = only drive when selected; '1' = always drive
RW 0' = only drive when selected; '1' = always drive
RW When '0', tx_clav/tx_enb pins are in tri-state.
Zarlink Semiconductor Inc.
RW Puts TXA/RXA in PHY or SAR mode. '1'=PHY Mode; '0'=SAR
RW Puts TXB/RXB in PHY or SAR mode. '1'=PHY Mode; '0'=SAR
RW Puts TXA/RXA in UTOPIA Level 2 mode. This disables port B
RW Reserved. Must always be “0000”
TS Reserved. Must always be “0”.
MT90502
Mode.
Mode.
Mode.
and requires port A to be configured as PHY. '0' = Level 1; '1' =
Level 2.
DAT/PAR/SOC pins.
DAT/PAR/SOC pins.
DAT/PAR/SOC pins.
145
Description
Data Sheet