mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 38

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.2.2.4
PCM/ADPCM CPS-Packet Assembly Structures are located in internal TX TDM Control Memory. Each PCM or
ADPCM channel will find an entry to its CPS-Packet Assembly Structure by the xxPCM Channel Number assigned
in the TX CAM.
#EDU: The number of EDUs per PCM CPS-Packet assembled. “000” = 1 EDU, “001” = 2 EDUs; “010” = 3
EDUs; “011” = 4 EDUs; “100” = 5 EDUs; “101” = 44/88 frame PCM/ADPCM; “110” = 40/80 frame
PCM/ADPCM; “111” = 8 EDUs.
Compression: “000” = PCM; “001” = ADPCM 40 kbps; “010” = ADPCM 32 kbps; “011” = ADPCM 24 kbps;
“100” = ADPCM 16 kbps; “101” = ADPCM auto-detect; “110” = PCM & ADPCM auto-detect (TDM
Format B must be chosen); “111” = reserved.
Partial Byte Storage[7:x] / Phase[3]: Used by hardware to store ADPCM samples that have not formed
complete bytes yet. When #EDU indicates 44/88-frame or 40/80 frame mode, the partial byte requires only 4
CPSP Buf
RP
overflows.
Written to ‘1’ any time the CPSP Buf RP is written.
S: Silent Bit. Indicates if the current CPS-Packet is silent so far or not.
SS: Silence Suppression. “000” = no silence suppression; “001” = associated odd stream bit represents
silence; “010” = A Match; “011” = B Match; “100” = silence indicated as in Fig 10; others = reserved
Sub Phase : Phase alignment of the channel within the 8 sub-phases possible in an EDU.
Phase[3:0]: Phase alignment of the channel among the different EDUs it may contain. This number
ranges between 0 and #EDU field. When #EDU is 44/88-frame packets are assembled every 44 or 88
frames. Phase and sub-phase specify where assembly should start for 88 frame packets and when
assembling 44 frame packets one will begin on the specified phase/sub-phase and another will begin 44
frames later by default. Therefore, there are eleven (0-10) phases in 44/88 frame mode. Similarly in
40/80 frame mode there are ten (0-9) phases. Bit 3 of the phase is encoded in Partial Byte
Storage[1].
RPV : Indicates that the CPSP Buf RP is valid, and thus that Circular Buffer Overflows can be detected.
Index of structure given by PCM Channel number in TX CAM.
Structures are located in internal TX TDM Control Memory (8000h to BFF0h).
bits (ADPCM-32) and is stored in bits 7:4. The LSB contains Phase[3] (programed by the CPU/Software).
Fields in Italic are used by hardware
Fields in Plain are written to by the CPU/Software.
Each structure is 16-bytes in size.
Note: The write pointer to the xxPCM Circular Buffers is global. Different write pointers exist for each
compression type and phase.
PCM/ADPCM CPS-Packet Assembly Structure
+0
+2
+4
+6
+8
: TX SAR’s pointer of up to where it has read in the channel’s circular buffer. Used to detect
b15
# EDU
b14
Figure 12 - PCM/ADPCM CPS-Packet Assembly Structure
b13
PCM/ADPCM CPS-Packet Assembly Structure
b12
Comp
b11
TX TDM Control Memory
b10
only.
b9
0
Zarlink Semiconductor Inc.
b8
S
0
MT90502
b7
CPSP Buf RP [7:1]
Partial Byte Storage[7:x] / Phase[3]
38
b6
b5
Sub Phase Phase[2:0]
b4
b3
b2
b1
SS
RPV
b0
0
Reserved
Data Sheet