mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 37

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

The MT90502 has the capability of aligning the transmission of PCM and ADPCM CPS-Packets containing the
same number of EDUs and destined to the same VC in order to obtain less delay and higher bandwidth efficiency.
To accomplish this, the phase and sub-phase fields of the PCM/ADPCM CPS-Packet assembly structure must
match the phase and sub-phase field of all other channels that are to be phase aligned on the same VC.
Programming the phase and sub-phase fields is done by the CPU upon configuration of the CPS-Packet assembly
structure.
By default, all phase and sub-phase counters are free running. Each counter picks up an arbitrary frame as phase
0 or sub-phase 0, then starts its counting. The phasing information, e.g. which frame is phase 0 and sub-phase 0, is
internal to the device in this case.
For certain applications some external devices must be aware of what phase and sub-phase the current frame
represents, so that they can know where the CPS-Packet boundary is. An example is ADPCM compressor which
should only change its compression rate at CPS-Packet boundaries. To indicate a CPS-Packet boundary a phasing
TSST structure is introduced to allow an external device to send phasing information to the MT90502. Once a
TSST is configured as phasing channel in TX CAM, the data on that TSST will overwrite internal counter(s). When
the MT90502 sees a 00h on that TSST, it takes that frame as phase 0 and sub-phase 0. When there is a 01h, it
interprets it as phase 0 sub-phase 1, and so on. The external device driving a phasing channel must ensure that a
proper counting pattern appears on this channel every frame.
Up to four phasing channels can be created, each with a different XPI value. When loading data to internal
counters, extra MSBs will be truncated. For example using a XPI value of ‘10’, a counting pattern of 0 to 63 also
serves as two cycles of 0 to 31, during which two 4-EDU CPS-Packets will be assembled.
XPI
00
01
10
11
Counting Pattern
0 to 23
0 to 39
0 to 63
0 to 87
#EDU = 3
#EDU = 5, and 40/80 frame PCM/ADPCM
#EDU = 1, 2, 4, 8
#EDU = 44/88 frame PCM/ADPCM
Table 18 - XPI Selection Table
Zarlink Semiconductor Inc.
MT90502
37
Replacing Internal Counters
Data Sheet