mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 69

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

MT90502
Data Sheet
Figure 33 - CPS-Packet Descriptor Queue Structures (HDLC Streams)
As HDLC supports streams, numerous channel packet descriptor queues can be amalgamated into one packet
descriptor per stream. However, it is necessary to specify the length of the packet descriptor queue within the
structure that manages the stream; therefore, the MT90502 can determine where to wrap its read and write
pointers. The length of the packet descriptor queue is programmed by the CPU/Software in the HDLC control
structure (see Figure 30, “RX TDM Control Memory Structure (PCM/ADPCM channels),” on page 66). The
CPS-Packet disassembly structures in the RX SAR determine where the HDLC channels are destined.
In HDLC, time slot entries in the linked list can point to the same control structure entry, allowing the HDLC
single-channel or stream to span consecutive time slots within the same TDM stream. This is employed for HDLC
streams where the bandwidth requirements often exceed the constraints of a single time slot. Since multiple entries
pointing to the same HDLC channel must all be contained within the same TDM stream, the maximum number of
time slots that can be shared by the same HDLC channel is 128.
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Zarlink Semiconductor Inc.