mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 67
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mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
(204 pages)
- Current page: 67 of 204
- Download datasheet (2Mb)
RX TDM Control Memory structures for HDLC Streams are located in internal memory at addresses C000h to FFF0h.
CPS-Packet Disassembly
Structure Number: Pointer to the AAL2 channel associated with this HDLC stream. This field is used to locate the RX Circular Buffer in
CPSPDQ Length:
Local WP/RP
and Fetch WP:
CPSPDQ RP/WP:
CPSP Read End
of Packet Pnt:
Negative Offset:
+10h
+12h
+14h NO7
+16h
+18h NO7
+20h
+22h
+24h NO7
+26h
+28h NO7
+30h
+32h
+34h NO7
+36h
+38h NO7
+40h
+42h
+44h NO7
+46h
+48h NO7
+0h
+2h
+4h
+6h
+8h
b15
Local RP
b14
Reserved
CPS-Packet Disassembly Struct Num
Negative Offset [5;0]
Negative Offset [5:0]
Negative Offset [5:0]
Negative Offset [5:0]
Negative Offset [5:0]
Negative Offset [5:0]
Negative Offset [5:0]
Negative Offset [5:0]
SSRAM.
Packet Descriptor Queue Length. Set to the number of timeslots in the stream. 01h = 1 TSST, 02h = 2 TSST, Max
size is 128.
Pointer to the pre-fetched HDLC packet handles contained in the 2/3/4/channel add on and the 5+ channel add-on.
They must be initialized to 0h by software on HDLC stream start-up.
Read/write pointer to this HDLC stream’s Packet Descriptor Queue (PDQ) in SSRAM.
Pointer to the last octet in HDLC packet in the RX Circular Buffer.
Current negative offset from the end of packet pointer at which the next byte of the HDLC packet will be read.
b13
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
CPS-Packet Dis Struct Num
Figure 31 - RX TDM Control Memory Structure (HDLC Streams)
RX TDM Control Memory Structure (HDLC Streams)
b12
Fetch WP
CPSPDQ RP [11:0]
CPSPDQ WP [11:0]
b11
b10
b9
Local WP
Zarlink Semiconductor Inc.
b8
Fields in Italic are used by the Hardware only.
Fields in Plain are written to by the CPU/Software.
[9:0]
MT90502
CPSP Read
CPSP Read
CPSP Read
CPSP Read
CPSP Read
CPSP Read
CPSP Read
CPSP Read
CPSP Read End of Packet Pnt [9:0]
b7
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
[9:0]
67
b6
b5
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
End of Packet Pnt [9:0]
Negative Offset [6:0]
b4
CPSPDQ Length [7:3]
b3
CPSPDQL [2:0]
b2
b1
b0
0
Second HDLC structure
Base HDLC structure
for all HDLC Streams
on a HDLC stream
Third and up to N
successive HDLC
structures on a
HDLC stream
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