mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 78

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.7.2
There are four classes of signals on the H.100/H.110 CT-Bus: Core, Compatibility, Optional, and Reserved signals.
Core, Compatibility, and Reserved signals are required for all H.100/H.110 compatible devices. These signals are
described in Table 26, “CT-Bus Signalling Function,” on page 78.
2.7.3
The H.100/H110 interface can sample the incoming data on the ct_d[31:0] at different sampling points: 2/4, 3/4 or
4/4 sampling. The desired sampling point can be set by setting the timing configuration register (732h). When
transmitting data, the H.100/H.110 can tri-state its pins between 20 ns and 0 ns before the rising edge of the clock
or it can tri-state synchronously on the rising edge of the clock. Both of these options allow flexibility in compatibility
with other devices that are not fully H.100/H.110 compliant.
2.7.4
Two clocks, A and B, can be configured to set one clock as primary bus master and the other one as backup
master. In the event of primary clock failure, the interface can switch over to backup. The MT90502, when operating
Core
Compatibility
Optional
Reserved
Class
Bus Signalling
H.100/H.110 Slave
Operating as a Slave
FR_COMP
CT_FRAME_A
CT_C8_A
CT_FRAME_B
CT_C8_B
CT_D[31:0]
CT_NETREF
SCLK
SCLKx2
C2
C4
C16+, C16-
CT_MC
CT_+5Vdc
Signal
Table 26 - CT-Bus Signalling Function
Frame Synchronisation, driven by the “A” clock master.
Bit clock driven by the “A” clock master.
Configurable frame synchronisation, driven by the “B” clock master.
Configurable bit clock - driven by “B” clock master.
Serial Data lines that collectively carry 32 signals and are referred to as the CT_D
bus. Each signals contain 128 time slots per frame at a clock frequency of
8.192 MHz.
Secondary network timing reference, providing backup network synchronisation to
the CT Bus.
Compatibility frame pulse, driven by current clock master, that serves as the frame
synchronization signal for the SCBus (Fsync*) and MVIP (F0) signals.
SCBus system clock, driven by current clock master. The signal is selectable (2, 4,
or 8 MHz) and is used to identify the data bits positions on the SCBus.
SCBus system clock times two, driven by clock master.
MVIP-90 bit clock, driven by current clock master. The clock frequency is 2 MHz,
nominally symmetrical.
MVIP-90 bit clock times two, driven current by clock master. The clock frequency
is twice C2, and transitions of C2 are synchronous with the falling edge of C4.
H-MVIP 16 MHz Clock, driven by current clock master. This differential signal is
used to read and write bits on the serial data lines by H-MVIP boards.
Message Channel for inter-device communication. This signal is terminated on
each CT Bus interface in the system which has message bus capability.
Provides power to active transition devices (cable adapters).
Signals reserved for future use.
Zarlink Semiconductor Inc.
MT90502
78
Function
Data Sheet