mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 47

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.3
2.3.1
The purpose of the TX SAR Module is to assemble AAL2 CPS-Packets into AAL2 ATM cells to be transmitted to the
UTOPIA Module. The TX SAR Module has no external interfaces, and does not control any of the MT90502's pins.
However, it is the connecting block between the Tx TDM module and the UTOPIA Module in the data transmission
direction.
2.3.2
The AAL2 cell assembly process is directed by the TX AAL2 VC Structure (see Figure 19 on page 47). This
structure is referenced and references all the structures necessary to compile an AAL2 ATM cell. It is employed by
the TX SAR module to raise an event for an AAL2 ATM cell. It constructs the ATM cell payload by referencing the
CPS-Packets via the CPS-Packet Descriptor Queue (SDRAM), which contains the CPS-Packet addresses in the
CPS-Packet Circular Buffer (TX SSRAM). The structure also contains the ATM header data, time-out data, next
CPU transmit CPS-Packet pointer, UTOPIA port destination and a free running counter of transmitted ATM cells.
It is the responsibility of the software to program the following in the TX AAL2 VC Structure (Figure 19).
•
•
•
The TX AAL2 VC Structures are of fixed size and are located at the beginning of the TX SSRAM memory space (+0000h) through to addresses +0FE0h,
+1FE0h, +3FE0h and +7FE0h for 128, 256, 512 and 1023 channels respectively.
Each structure is 32 bytes in size.
Fields in Plain are written to by the CPU/Software.
Fields in Italic are used by Hardware only.
+7FC0h
+7FE0h
time-out period
ATM header associated with the VC
the TXD (TX Destination) field
+00h
+20h
The number of VC Structures in
this table can be programmed to
{128, 256, 512, 1023}
TX SAR
Overview
AAL2 Cell Assembly Process
Relative Mapping in
SRAM Memory
VC Number 1022
VC Number 1023
VC Number 0
VC Number 1
Figure 19 - TX AAL2 VC Structure
+0h
+2h
+4h
+6h
+8h
+Ah
+Ch
+Eh
+10h
+12h
Zarlink Semiconductor Inc.
MT90502
b15
PS SA
V
Packet Descriptor Read Pointer[8:0]
Packet Descriptor Write Pointer[8:0]
b14
TXD
47
b13
TX AAL2 VC Structure
b12
CPU Sourced CPS-Packet Control[16:1]
b11
Transmitted Cell Count[31:16]
Transmitted Cell Count[15:0]
Pending Packet Timeout Period[13:0]
Cell Expired Time-stamp
b10
b9
Header[31:16]
Header[15:0]
b8
b7
b6
Pending Pay load Bytes
Current Packet Offset[6:0]
b5
b4
b3
Reserved
b2
b1
b0
Data Sheet