mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 70

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.6
2.6.1
The purpose of the UTOPIA module is to provide an external interface with the ATM domain. The MT90502
complies with the ATM Forum's specifications: af-phy-0017.000 (PHY & SAR) and af-phy-0039.000 (PHY).
The UTOPIA module is responsible for accepting cells from five input interfaces: UTOPIA A, UTOPIA B, UTOPIA C,
CPU Origin Data Cell FIFO, and TX SAR (internal). Cells are examined, and based on the origin and information in
the header, the cell is sent to one or more (multicast or broadcast) of the four output interfaces: UTOPIA A, UTOPIA
B, UTOPIA C or RX SAR (internal). The UTOPIA module employs octet level handshaking. It also appends the
HEC to outgoing ATM cells.
The UTOPIA module has 2 different configurations and is constructed from three ports, labelled A, B, and C.
•
•
In addition to ports A, B, and C, the UTOPIA can route data cells to the cell FIFO in external SSRAM.
The receive interface of each UTOPIA port can be independently enabled or disabled. If disabled, the receive
interface will stop accepting cells after the current cell has been received.
The transmit interface of each UTOPIA port can be configured to drive output pins (e.g., data bus, SOC and parity)
only when this port has been selected. Those pins are tri-stated when the port is not selected. This allows the
MT90502 to share a data bus, SOC, and parity lines with other devices (i.e., independent ENB signals and CLAV
signals for each PHY device, controlled by a single ATM device).
RXA
UTOPIA
RXB
UTOPIA
RXC
UTOPIA
Each UTOPIA port (A, B or C) can be independently configured as a 8-bit Level 1 PHY or ATM port, and
can operate at up to 32 MHz. In this configuration, ports can be employed to daisy-chain other SAR
devices to the MT90502, or operate in a ring configuration. Each port can treat 155 Mbps of bandwidth.
Ports A and B can also be combined to architect one UTOPIA Level 2 port in PHY mode only. It has an
8-bit data bus and a 5-bit address bus. This configuration allows the MT90502 to interface with any
UTOPIA Level 2 master device in a multiple-PHY application.
UTOPIA
Overview
4 Cell
input
FIFO
4 Cell
input
FIFO
4 Cell
input
FIFO
(64K to 512K VCs/Port)
LUT in SDRAM
64 Cell
output
FIFO
Figure 34 - SAR and UTOPIA Block
Data Cell FIFO in
SSRAM
(4KB to 128KB)
Zarlink Semiconductor Inc.
RX SAR
ATM Cell to
CPS-Packet
Disassembly
MT90502
70
TX SAR
CPS-Packet
to ATM Cell
Assembly
CPU Origin
Data Cells
4 Cell
input
FIFO
4 Cell
input
FIFO
16 Cell
output
FIFO
16 Cell
output
FIFO
16 Cell
output
FIFO
Data Sheet
TXC
UTOPIA
TXA
UTOPIA
TXB
UTOPIA