mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 14
mt90502ag2
Manufacturer Part Number
mt90502ag2
Description
Multi-channel Aal2 Sar
Manufacturer
Zarlink Semiconductor
Datasheet
1.MT90502AG2.pdf
(204 pages)
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The following tables contain each pin of the MT90502’s main functional areas. A description of each pin is also
provided.
Notes:
•
•
•
•
•
•
•
•
1.1
AC3
F25, F23, J24, J23
AA3, AA4, Y1, Y2, Y3,
Y4, W1, W2, W3, W4,
V1, V2, V3, V4, U1
T2
T1
U4
T4
U3
T3, R1, R2, R3, R4, P1,
P2, P3, P4, N1, N2, N3,
N4, M1, M2, M3
U2
AC2
AC1
C21
A19
D21
All outputs are +3.3 V
All input and output pins that are designated (F) can withstand 5 V
All input and output pins that are designated (F) are tested with a 50 pF load unless otherwise specified.
Designations under the “rst” (reset condition) table column are: X = undefined; Z = high impedance; 1 =
high (+3.3 V
I/O types include: Output (O), Input (I), Bidirectional (I/O), Power (PWR) and Ground (GND).
All buses have pins listed in order from MSB to LSB.
Pins with more than one function have their functions numbered.
Unused H.100/H.110 input pins should be tied high with an external pull-up.
Pin Description Tables
Pin
Pins
DC
).
rst
Z
Z
Z
Z
DC
upclk
cpu_mode[3:0]
cpu_a[14:0]
cpu_wr_r/w
cpu_rd_ds
cpu_ale
cpu_a_das
cpu_cs
cpu_d[15:0]
cpu_rdy_dtack
interrupt1
interrupt2
.
rst
Z
Z
Name
txa_led
rxa_led
rxa_alarm
Table 2 - UTOPIA Interface Pins
Table 1 - CPU Bus Interface
Name
I/O
I/O
I/O
O
O
I
I
I
I
I
I
I
I
Zarlink Semiconductor Inc.
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
LVTTL 6 mA (F)
MT90502
14
Type
I/O
I/O
I/O
I
LVTTL 12 mA (F)
LVTTL 12 mA (F)
LVTTL (F)
CPU Clock.
CPU Interface Mode Select (4 bits).
CPU Address bus.
Intel Write or Motorola Read/Write
Intel Read or Motorola Data Strobe
Address Latch Enable
Direct Access Select. ‘1’ selects the direct address
space. ‘0’ selects the indirection registers
contained in the CPU interface. This pin can be
connected to the MSB of an address bus.
CPU chip select
CPU Data bus
Intel Ready or Motorola Data Ack.
Interrupt 1 (configurable polarity)
Interrupt 2 (configurable polarity)
Type
DC
being applied to them.
UTOPIA port A TX LED
UTOPIA port A RX LED
UTOPIA port A PHY alarm
Description
Description
Data Sheet
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