mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 83

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.8
2.8.1
The purpose of the clock recovery module is to synchronize the TDM clock domain of the MT90502 with other
devices on the network through information transmitted across the ATM link. Clock recovery is necessary only
when the MT90502 is operating as the TDM clock master.
The clock recovery system is composed of several sub-components:
2.8.1.1
These modules generate data on a regular basis which is written to external memory for the CPU to read and is
used by the clock recovery algorithm. Counts of mem_clk and adapx_ref clock, as well as the current UUI and LI
values, associated with the current cell, are placed in external memory.
adapx_ref clock generation
These modules divide mem_clk to a desired frequency with a 16-bit integer and 16-bit fraction. These 32 bits are
normally determined by the clock recovery algorithm.
2.8.1.2
There are eight general purpose I/Os as well as two ct_netref pins. Each has the ability to multiplex one of 23
signals as outputs.
2.8.2
The MT90502 has two clock recovery modules, A and B. Each module receives pulses obtained either from the
UTOPIA module (timing reference VCs) or from the Rx SAR (timing reference CPS-Packets). The signals
clkrecov_pulse_a and clkrecov_pulse_b come from one of these modules. The modules which generate the A and
B clkrecov_pulses are configured by the A and B bits. These are configured in the UTOPIA section for timing
reference VCs or in the Rx SAR section for timing reference CPS-Packets. The VC/CPS-Packet designated A is
the timing reference for the A clock recovery module (clkrecov_pulse_a). Similarly, for the B clock recovery module,
the clkrecov_pulse_b is generated by the VC/CPS-Packet designated by its B bit.
Running in parallel, are counters of the mem_clk and adapx_ref signals. A clock recovery event structure is written
to external memory with the arrival of every X pulses of clkrecov_pulse_x. The structure (see Figure 46 on page 84)
is composed of the 32-bit “mem_clk” counter, the 32-bit “ref” counter, a 16-bit
“mem_clk_cycles_since_last_ref_increment” counter (fraction of the ref), as well as the LI and UUI of the received
CPS-Packet. These event structures are written to a buffer in external memory, and the clock recovery module will
generate an interrupt when the buffer is more than half full (if enabled in bit 10 of register 210h). Clock recovery
events arrive at a fixed rate, therefore the size of the buffer chosen (820h, 828h Table 31, “Buffer Sizes,” on
page 90) will completely determine the rate at which it needs to be serviced. To decrease the number of points
written to memory, program the keep_one_pulse_out_of_x register (710h & 718h see Table 30, “Clock Recovery
Registers,” on page 88) to a value greater than 1.
Clock Recovery
Overview
Adaptive Clock Recovery Modules
Adaptive Clock Recovery Modules
Multiplexers
Zarlink Semiconductor Inc.
MT90502
83
Data Sheet