mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 75

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.6.6
Each of the three ports must have a clock to operate the receive interface and a clock to operate the transmit
interface. Two or more clocks may have the same source. These clocks can either be input to the MT90502 from an
external source or output from the MT90502 from one of three internal UTOPIA clocks. However, the receive clock
and transmit clock for a port can either be set as an input or an output.
The source of each of the three internal UTOPIA clocks can be one of seven clocks: mem_clk, or any of the six
UTOPIA clocks (rxa_clk, rxb_clk, rxc_clk, txa_clk, txb_clk, and txc_clk). The selected clock is divided by n and can
be inverted (register 220h).
The maximum speed of UTOPIA clock is 32 MHz.
Other parts of the UTOPIA module, including the look-up engine, the TX_SAR portion, and the RX_SAR portion
operate off of mem_clk.
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13
Notes:
•
•
•
All three ports have
independent parameters
(vci_nx, LUT Base
Address).
result is a pointer, offset
from the LUT Base
Address, to the first byte
of the LUT entry.
LUT Entry Address
represents a byte
address
UTOPIA Clocks
b23 b22 b21 b20b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
VPI
Figure 38 - VPI/VCI Concatenation and LUT Entry Address Example
b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3
b10
Zarlink Semiconductor Inc.
b12
LUT Entry Address
MT90502
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
75
Σ
VCI
b23. . . . . . . . . . . . . . . . . . . . . .. . ..20
Port A LUT Base Address (reg. 620h)
b1
vci_na (reg. 622h) = 5 VCI Bits
Concatenated VPI and VCI
b19 . . . . . . . . 0
0......................0000
b2 b1 b0
0 0 0
Data Sheet