mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 71

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.6.2
Each of the three ports are divided into two portions: a receive portion and a transmit portion. The TX_SAR and the
receive portions are each connected to a 4-cell FIFO.
The RX_SAR and the transmit portions are each connected to a 16-cell FIFO.
The ports are configurable with the following options:
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*Not applicable when Port A and B are configured as level-2 multi-PHY port.
The RX_CLAV signal is asserted high any time a complete cell can be received. Thus as soon as the first byte of a
cell is received, and there is no room for another cell in the input FIFO, the RX_CLAV signal will be asserted low. In
the case of a Level-2 PHY, the rx_clav's will only be driven when the address has been placed on the bus during the
previous cycle.
2.6.3
The UTOPIA module generates four LED signals in order to indicate the status of each of the possible conditions
for the A and B ports. The status conditions are: idle, presence of traffic or PHY alarm. When a port is in an idle
state, both its LEDs are illuminated. If RX traffic (other than null cells) is flowing, then the RX LED for that port will
flash; If TX traffic (other than null cells) is flowing, then the TX LED for that port will flash. If a PHY alarm is detected,
the TX LED is static on and the RX LED is static off. The polarity of the LED signals is active-low, i.e., a ‘0’ will turn
on the LED.
The frequency of the LEDs is controlled in register 10Ch and the LED pins can also be configured to act as general
purpose input outputs.
The PHY alarm is another testing feature. If a PHY device connected to the MT90502 indicates a trouble with the
PHY (through pins rxa_alarm or rxb_alarm), the MT90502 acknowledges receipt of the information by setting the
LEDs appropriately (see above). The alarm causes no change in the MT90502, other than from setting the LEDs.
2.6.4
If the MT90502 receives a short cell on any one of its three ports, the cell is discarded and the next cell is started
when the second SOC signal is set.
If the SOC is not set after the 53rd byte of a received cell, subsequent bytes are ignored until a new SOC is
received.
Port A's transmit portion can be ATM or PHY, with an 8-bit data bus.*
Port A's receive portion can be ATM or PHY, with an 8-bit data bus.*
Ports A and B can be combined to architect one UTOPIA Level 2 multi-PHY port, with an 8-bit data bus.
Port B's transmit portion can be ATM or PHY, with an 8-bit data bus.*
Port B's receive portion can be ATM or PHY, with an 8-bit data bus.*
Port C's transmit portion can be ATM or PHY, with an 8-bit data bus.
Port C's receive portion can be ATM or PHY, with an 8-bit data bus.
Each receive interface can be independently enabled or disabled. If disabled, the receive interface will stop
accepting cells after the current cell has been received.
When the transmit portions of a port are in PHY mode, the SOC, data bus, and parity output pins will be
tri-sected when the port is not selected. This allows the MT90502 to share a data bus, SOC, and parity lines
with other devices (i.e., independent ENB signals and CLAV signals for each PHY device, controlled by a
single ATM device).
UTOPIA Interfaces
LED Operation
Errors on Received Cells
Zarlink Semiconductor Inc.
MT90502
71
Data Sheet