mt90502ag2 Zarlink Semiconductor, mt90502ag2 Datasheet - Page 49

• Manufacturer Part Number: mt90502ag2
• Description: Multi-channel Aal2 Sar
• Manufacturer: Zarlink Semiconductor

2.3.2.1
•
•
•
•
•
•
•
•
•
•
•
•
Header[31:0]
Transmitted Cell
Count
CPU Sourced
CPS-Packet
Control
The CPS-Packet Assembly Structure raises a CPS-Packet event upon the alignment of the sub-phase
and phase (See Figure 12 - PCM/ADPCM CPS-Packet Assembly Structure).
The CPS-Packet Assembly Structure is mapped to the CPS-Packet Final Assembly Structure by the
absolute address of both structures.
The CPS-Packet Final Assembly Structure reads the ‘CPS-Packet Descriptor Write Pointer’ in the AAL2
VC Structure to determine the next address to write the current CPS-Packet.
The CPS-Packet Assembly Structure retrieves the payload data from the TX TDM Frame Buffer and
writes it to the CPS-Packet Circular Buffer in TX SSRAM.
In preparation for the next CPS-Packet, the CPS-Packet Final Assembly Structure then updates (i.e.
writes) the ‘Packet Descriptor Write Pointer’ in the ‘AAL2 VC Structure’.
The ‘Pending Payload Byte’ field is updated by the TX TDM module when a CPS-Packet event is raised.
When more than one CPS-Packet event is raised within the same CT_FRAME, each CPS-Packet event
generates its corresponding CPS-Packets Final Assembly Structure in the TX TDM process. The TX
SAR sequentially steps through each CPS-Packet Final Assembly Structure and for each process
consults the associated AAL2 VC Structure to determine if enough payload has accumulated to generate
a VC Send Event (see Figure 20, “Cell Assembly Event Queue,” on page 50). If enough payload is
present then the TX SAR raises a VC Send Event and updates the Pending Payload Byte field with the
remaining number of pending payload bytes. However, a VC Send Event may also be generated via the
time-out period specified in the AAL2 VC Structure. All VCs have a time-out period that specifies the
maximum time that any CPS-Packet destined to that VC can wait before a cell containing them is
assembled. The time-out period is defined in CT Frames (i.e., multiples of 125 µs) in the AAL2 VC
Structure.
The ATM header information is contained within the AAL2 VC Structure.
The Packet Descriptor Read Pointer in the AAL2 VC Structure points indirectly to the complete
CPS-Packet via the CPS-Packet Base Address in the Descriptor of the CPS-Packet Descriptor Queue.
The CPS-Packet Descriptor Queue contains Descriptors for each complete CPS-Packet. The
Descriptors contained the CPS-Packet header information and the absolute address of the CPS-Packet
in the TX SSRAM.
The VC Number in the CPS-Packet Final Assembly Structure points to the VC Send Event structure. A
VC Send Event structure is only generated when enough payload is obtained to fill an ATM cell or the
cell has past the expiry period. This is denoted by the Pending Payload Byte or Cell Expiry Time Stamp
field in the AAL2 VC Structure.
Upon a VC Send Event, the TX SAR writes a complete ATM cell (see Figure 21 on page 50) to the TX
SAR Input FIFO (4 cell depth).
Field
AAL2 Cell Assembly Procedure
Byte Address
Offset/Bits
+10/b[15:0]
+12/b[15:0]
+A/b[15:0]
+C/b[15:0]
+E/b[15:0]
Used
Table 21 - AAL2 VC Structure Fields (continued)
ATM Cell Header in the following order (starting from bit 31): GFC,
VPI, VCI, PT, CLP
Free running transmitted cell counter.
This field points to the first word of the next CPU sourced
CPS-Packet.
Zarlink Semiconductor Inc.
MT90502
49
Description of Field
Data Sheet