IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 105

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: Performing SignalTap II Logic Analysis
SignalTap II Example Designs
Specifying the Trigger Levels
Performing SignalTap II Analysis
© June 2010 Altera Corporation
3. Select a depth of 128 for the SignalTap II sample buffer (that is, the number of
4. Verify that the Use Base Clock option is on.
5. Click the Simple tab and verify that the Use Board Block to Specify Device
6. Click the Compile button.
7. Click Scan Jtag and select the appropriate download cable and device (for
8. Click Program to download your design to the development board.
9. Click OK.
To specify the trigger levels, follow these steps:
1. Double-click the SignalTap II Logic Analyzer block. The dialog box
2. Specify the following trigger condition settings for the firstandout block:
3. Repeat these steps to specify the trigger condition High for the secondandout
The SignalTap II logic analyzer captures data for analysis when it detects all trigger
patterns simultaneously on the input signals. For example, because you specify
Falling Edge for firstandout and High for secondandout, the SignalTap II logic
analyzer only triggers when it detects a falling edge on firstandout and a logic
level high on secondandout.
You are now ready to run the analyzer and display the results in a MATLAB plot.
After you click Acquire, the SignalTap II logic analyzer begins analyzing the data and
waits for the trigger conditions to occur. To perform analysis, follow these steps:
1. Click Scan Jtag in the SignalTap II Logic Analyzer dialog box and select the
2. Click Acquire.
samples stored for each input signal) in the SignalTap II depth list.
option is on.
When the conversion is complete, information messages in the dialog box display
the memory allocated during processing.
1
example, USB-Blaster cable and EP2C35 device).
displays all the nodes connected to SignalTap II Node blocks as signals to be
analyzed.
a. Click firstandout under Signal Tap II Nodes.
b. Select Falling Edge in the Set Trigger Level list.
c. Click Change. The condition is updated.
block.
appropriate download cable and device.
You must compile your design before you open the SignalTap II
Analyzer block because the block relies on data files that create during
compilation.
Preliminary
DSP Builder Standard Blockset User Guide
6–7