IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 310

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–2
AltBus
Table 6–1. AltBus Block Parameters
Table 6–2. AltBus Block I/O Formats
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Saturate Output
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
Name
[L1].[R1]
Simulink (2),
[LP].[RP]
Table
is an input port. O1
6–2:
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
(Parameterizable)
(Parameterizable)
On or Off
(3)
The AltBus block modifies the bus format of a DSP Builder signal. Only use this
block as an internal node in a system, not as an input to or output from the system. If
the specified bit width is wider than the input bit width, the bus is sign extended to
fit. If it is smaller than the input bit width, you can specify to either truncate or
saturate the excess bits.
Table 6–1
Table 6–2
Table 6–3
(4/3 = 1.3333) is cast into signed binary fractional format with three different binary
point locations.
Table 6–3. Floating-Point Numbers Cast to Signed Binary Fractional
Note to
(1) In this case, more bits are needed to represent the integer part of the number.
[L].[R]
Value
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
Bus Notation
is an output port.
Table
[4].[1]
[2].[3]
[1].[4]
shows the AltBus block parameters.
shows the AltBus block I/O formats.
and
6–3:
(Note 1)
Figure 6–1 on page 6–3
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This parameter
applies only to signed fractional buses.
When this option is on, if the output is greater than the maximum positive or
negative value to be represented, the output is forced (or saturated) to the
maximum positive or negative value, respectively. When off, the MSB is truncated.
Preliminary
Input
4/3
4/3
4/3
VHDL
illustrate how a floating-point number
Description
-0.6875
Simulink
1.00
1.25
(1)
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Implicit - Optional
Explicit
VHDL
Type
-11
10
2
(4)
AltBus