IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 23

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Design Flow
© June 2010 Altera Corporation
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This chapter describes the design flow and a tutorial.
When using DSP Builder, you start by creating a Simulink design model in the
MathWorks software. After you have created your model, you can compile directly in
the Quartus II software, output VHDL files for synthesis and Quartus II compilation,
or generate files for VHDL simulation.
DSP Builder generates VHDL and does not generate Verilog HDL. However, after you
have created a Quartus II project, you can use the quartus_map command in the
Quartus II software to run a simulation netlist flow that generates files for Verilog
HDL simulation.
For information about this flow, refer to the Quartus II help.
Preliminary
DSP Builder Standard Blockset User Guide
2. Getting Started