IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 269

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
Decoder
Decoder
Table 4–11. Decoder Block Parameters
© June 2010 Altera Corporation
Input Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Register Output
Decoded Value
Name
1
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
On or Off
User defined
(Parameterizable)
end process;
The Case Statement block output ports in the VHDL are named r<number>
where <number> is auto-generated.
The Decoder block is a bus decoder that compares the input value against the
specified decoded value. If the values match, the block outputs a 1, if they do not
match it outputs a 0.
If the specified value is not representable in the data type of the input bus, it is
truncated to the data type of the input bus. For example: 5 (binary 101) as a 2 bit
unsigned integer results in 1 (binary 01).
Table 4–10
Table 4–10. Decoder Block Inputs and Outputs
Table 4–11
in
match
Value
Signal
end case;
shows the Decoder block parameters.
shows the Decoder block inputs and outputs.
when "00000111" =>
when others =>
Input
Output
Turn this option on if you want to register the output result.
Specify the bus number format that you want to use.
Specify the number of bits to the left of the binary point.
Specify the number of bits to the right of the binary point for the gain. This
option is zero (0) unless Signed Fractional is selected.
Specify the decoded value for matching.
Direction
r1 <= '0';
r2 <= '1';
r3 <= '0';
r4 <= '0';
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '1';
r4 <= '0';
r0 <= '0';
r1 <= '0';
r2 <= '0';
r3 <= '0';
r4 <= '1';
Preliminary
Data input.
Data output (1 = match, 0 = mismatch).
Description
Description
DSP Builder Standard Blockset Libraries
4–7