IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 193

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: AltLab Library
Clock_Derived
Table 1–2. Clock Block Parameters
Clock_Derived
© June 2010 Altera Corporation
Real-World Clock Period
Period Unit
Simulink Sample Time
Reset Name
Reset Type
Export As Output Pin
Name
1
Table 1–2
Use the Clock_Derived block in the top level of a design to add additional clock
pins to your design. Specify these clocks as a rational multiple of the base clock for
simulation purposes.
DSP Builder uses the block name as the name of the clock signal. It must be a valid
VHDL identifier.
You can specify the numerator and denominator multiplicands calculates the derived
clock. However, the resulting clock period should be greater than 1ps but less than
2.1ms.
If no base clock is set in your design, DSP Builder creates a 20ns base clock and
determines the derived clock period. You must use a
if you want the sample time to be anything other than 1.
To avoid sample time conflicts in the Simulink simulation, ensure that the sample
time specified in the Simulink source block matches the sample time specified in the
Input block (driven by the
Each clock must have a unique reset name. As all clock blocks have the same default
reset name (aclr) ensure you specify a valid unique name with multiple clocks.
You can add reset synchronizer circuitry for this clock domain by specifying the reset
type to be synchronized active low or synchronized active high.
When you specify these reset types, DSP Builder adds two extra registers to avoid
metastability issues during reset removal.
Table 1–3
user specified
ps, ns, us, ms, s
> 0
User defined
Active Low,
Active High,
Synchronized
Active Low,
Synchronized
Active High
On or Off
lists the parameters for the Clock block.
lists the parameters for the Clock_Derived block:
Value
Specify the clock period, which should be greater than 1ps but less than
2.1 ms.
Specify the units for the clock period (picoseconds, nanoseconds,
microseconds, milliseconds, or seconds).
Specify the Simulink sample time.
Specify a unique reset name. The default reset is aclr.
Specify whether the reset signal is active high or active low.
Turn on to export this clock as an output pin.
Clock
Preliminary
block or a derived clock).
Description
Clock
DSP Builder Standard Blockset Libraries
block to set the base clock
1–3