IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 346

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–6
Table 9–9. Dual-Clock FIFO Block I/O Formats
Figure 9–3. Dual-Clock FIFO Block Example
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
O2
O3
O4
O5
O6
O7
[L].[R]
Simulink (2),
[L1].[R1]
[1]
[1]
[L1].[R1]
[1]
[1]
[1]
[1]
[L2].[0]
[L2].[0]
Table
is an input port. O1
9–9:
(3)
Table 9–9
Figure 9–3
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O2: out STD_LOGIC
O3: out STD_LOGIC
O4: out STD_LOGIC
O5: out STD_LOGIC
O6: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
O7: out STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
[L].[R]
is an output port.
shows the Dual-Clock FIFO block I/O formats.
shows an example with the Dual-Clock FIFO block.
(Note 1)
Preliminary
VHDL
© June 2010 Altera Corporation
Chapter 9: Storage Library
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit-optional
Explicit-optional
Type
Dual-Clock FIFO
(4)