IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 248

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–2
Butterfly
Table 3–2. Butterfly Block Parameters (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Input Bit Width (a, b, W)
Number of Pipeline Stages
Full Resolution for Output
Type
Output Bit Width (A, B)
Output Truncated LSB
W is constant
Name
The Butterfly block performs the following arithmetic operation on complex
signed integer numbers:
This function operates with full bit width precision. The full bit width precision of A
and B is:
The Output Bit Width and Output Truncated LSB parameters specify the bit slice for
the output ports A and B. For example, if the input bit width is 16, the output bit
width is 16, and the output LSB is 4, then the full precision is 34 bits and the output
ports A[15:0] and B[15:0] each contain the bit slice 19:4.
Table 3–1
Table 3–1. Butterfly Block Inputs and Outputs
Table 3–2
a
b
W
ena
aclr
A
B
A = a + b×W
B = a - b×W
where a, b, W, A, and B are complex numbers (type signed integer) such as:
2 × [input bit width] + 2.
Signal
a = x + jX
b = y + jY
W = v + jV
A = (x + yv) - YV + j(X + Yv + yV)
B = (x - yv) + YV + j(X - Yv - yV)
>= 1
>= 3
On or Off
>= 1
>= 0
On or Off
shows the Butterfly block inputs and outputs.
shows the Butterfly block parameters.
Value
Input
Input
Input
Input
Input
Output
Output
Direction
Specify the bit width of the complex signed integer inputs a, b, and W.
Specify the required number of pipeline stages.
When this option is on, full output bit width resolution is enabled. When off,
you can separately specify the output bit width and LSB of the output.
Specify the bit width of the complex signed integer outputs A and B. This
option is available when Full Resolution for Output Type is off.
Specify the LSB of the output bus slice of the full resolution computation.
This option is available when Full Resolution for Output Type is off.
When this option is on, you can specify the real and imaginary values for W
instead of the W port.
Preliminary
Data input a.
Data input b.
Optional input W.
Optional clock enable.
Optional asynchronous clear.
Data Output A.
Data Output B.
Description
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Butterfly