IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 25

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Getting Started
Design Flow
Figure 2–2. Configuration Parameters for Simulation
© June 2010 Altera Corporation
3. Set a discrete (no continuous states) solver in Simulink. Choose a Fixed-step solver
4. Simulate your model in Simulink using a Scope block to monitor the results.
5. Run Signal Compiler to setup RTL simulation and synthesis.
6. Perform RTL simulation. DSP Builder supports an automated flow for the
7. Use the output files generated by the DSP Builder Signal Compiler block to
8. Compile your design in the Quartus II software.
9. Download to a hardware development board and test.
For an automated design flow, the Signal Compiler block generates VHDL and Tcl
scripts for synthesis in the Quartus II software. The Tcl scripts let you perform
synthesis and compilation automatically in the MATLAB and Simulink environment.
You can synthesize and simulate the output files in other software tools without the
Tcl scripts. In addition, the Testbench block generates a testbench and supporting
files for VHDL simulation.
type if you are using a single clock domain or a Variable-step type if you use
multiple clock domains.
To set the solver options, click Configuration Parameters on the Simulation menu
to open the Configuration Parameters dialog box and select the Solver page
(Figure
f
ModelSim software (using the TestBench block). You can also use the generated
VHDL for manual simulation in other simulation tools.
perform RTL synthesis. Alternatively, you can synthesize the VHDL files manually
using other synthesis tools.
2–2).
For detailed information about solver options, refer to the description of
the “Solver Pane” in the Simulink Help.
Preliminary
DSP Builder Standard Blockset User Guide
2–3