IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 284

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

4–22
Figure 4–14. Multiplexer Block Example
Pattern
Table 4–38. Pattern Block Parameters (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Binary Sequence
Specify Clock
Clock
Name
1
The Pattern block generates a repeating periodic bit sequence in time. You can enter
the required pattern as a binary sequence.
For example, the pattern 01100 outputs the repeating pattern:
You can change the output data rate for a registered block by feeding the clock enable
input with the output of the Pattern block.
With a sequence of length 1, the Pattern block acts as a constant, holding its output
to the specified value at all times. There is no artificial limit to the pattern length.
Table 4–37
Table 4–37. Pattern Block Inputs and Outputs
Table 4–38
ena
sclr
<unnamed>
0110001100011000110001100011000110001100
Signal
User Defined
On or Off
User defined
(Parameterizable)
shows the Pattern block inputs and outputs.
shows the Pattern block parameters.
Value
Input
Input
Output
Direction
Specify the sequence that you want to use.
Turn on to explicitly specify the clock name.
Specify the name of the required clock signal.
Preliminary
Optional clock enable port.
Optional synchronous clear port.
Output data port.
Description
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Pattern