IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 325

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Output
Output
Table 6–28. Output Block Parameters
Table 6–29. Output Block I/O Formats
© June 2010 Altera Corporation
Bus Type
[number of bits].[] >= 0 (Parameterizable)
[].[number of bits] >= 0 (Parameterizable)
External Type
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
Name
[L1].[R1]
Simulink (2),
[LP].[RP]
Table
is an input port. O1
6–29:
Inferred, Signed Integer,
Unsigned Integer,
Signed Fractional,
Single Bit
Inferred,
Simulink Fixed Point Type,
Double
(3)
The Output block defines the output boundary of a hardware system and casts
signed binary fractional format (from DSP Builder blocks) to floating-point Simulink
signals (feeding generic Simulink blocks).
Output blocks map to output ports in VHDL and mark the edge of the generated
system. You normally connect these blocks to Simulink simulation blocks in your
testbench. Their outputs should not be connected to other Altera blocks.
You can optionally specify the external Simulink type. If set to Simulink Fixed
Point Type, the bit width is the same as the input. If set to Double, the width may
be truncated if the bit width is greater than 52.
Table 6–28
Table 6–29
[L].[R]
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
Value
is an output port.
shows the Output block parameters.
shows the Output block I/O formats.
(Note 1)
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the
sign bit. This parameter does not apply to single-bit buses.
Specifies the number of bits to the right of the binary point. This
parameter applies only to signed fractional buses.
Specifies whether the external type is inferred from the Simulink block it
is connected to or explicitly set to either Simulink Fixed Point or Double
type. The default is Inferred.
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Implicit - Optional
Explicit
Type
(4)
6–17