IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 89

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

HIL Design Flow
© June 2010 Altera Corporation
Adding the HIL block to your Simulink model allows you to cosimulate a Quartus II
software design with a physical FPGA board implementing a portion of that design.
You define the contents and function of the FPGA by creating and compiling a
Quartus II project. A simple JTAG interface between Simulink and the FPGA board
links the two.
The main benefits of using the HIL block are faster simulation and richer
instrumentation. The Quartus II project you embed in an FPGA runs faster than a
software-only simulation. To further increase simulation speed, the HIL block offers
frame and burst modes of data transfer that are significantly faster than single-step
mode when you use it with suitable designs.
The HIL block also makes available to the hardware a large Simulink library of sinks
and sources, such as channel models and spectrum analyzers, which can give you
greater control and observability.
This chapter explains the HIL block design flow, walks through an example using the
HIL block, and discusses the optional burst and frame data transfer modes.
The HIL block in AltLab library of the Altera DSP Builder Blockset enables the HIL
functionality. It represents the functions implemented on your FPGA, and works
smoothly with the normal DSP Builder/Simulink work flow.
The HIL design flow comprises the following steps:
1. Create a Quartus II project that defines the functions you want to co-simulate in
2. Add the HIL block to your Simulink model and import the compiled Quartus II
3. Specify parameters for the HIL block, including the following options:
4. Compile the HIL block to create a programming object file (.pof) for hardware
hardware and use Signal Compiler block to compile the Quartus II project
through the Quartus II Fitter.
project into the HIL block. You can also connect instrumentation to your HIL block
by adding additional blocks from the Simulink Sinks and Sources libraries.
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cosimulation.
The Quartus II project to define its functionality
The clock and reset pins
The reset active level
The input and output pin characteristics
The use of single-step versus burst and frame mode
If the original design contains a Clock block that defines a period and
sample time that is different from the default values, you must add a Clock
block with the same values as the HIL block.
Preliminary
DSP Builder Standard Blockset User Guide
5. Using HIL