IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 127

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 7: Using the Interfaces Library
Avalon-MM FIFO Design Example
© June 2010 Altera Corporation
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2. On the File menu in the Quartus II software, click New Project Wizard and set the
3. On the Tools menu, click Tcl Scripts and set the following options:
4. On the Tools menu, click SOPC Builder to display the Create New System dialog
5. Click the System Contents tab in SOPC Builder and set the following options:
6. Double-click the Nios II Processor module in the System Contents tab to display
7. Set the reset and exception vectors to use onchip_memory2_0 and click Finish to
8. Expand DSPBuilder Systems in the System Contents tab and double-click the
You can now design the rest of your NIOS embedded processor with the standard
SOPC Builder design flow.
For more detailed instructions, refer to
page 7–12
following options:
a. Specify the working directory for your project by browsing to <DSP Builder
b. Specify a name for your project. This tutorial uses FIFO for the project name.
1
c. Click Finish to create the Quartus II project.
a. Load your design by selecting sopc_edge_detector_add.tcl in the Project
b. Click Run.
box.
a. Specify AvalonFIFO as the system name.
b. Select VHDL for the target HDL.
c. Click OK.
a. Expand Memories and Memory Controllers.
b. Expand On-Chip and double-click On Chip Memory (RAM or ROM).
c. Click Finish to add an on-chip RAM device with default parameters.
the MegaWizard interface.
add the processor to your system with all other parameters set to their default
values.
sopc_edge_detector_interface module to include it in your Nios II system.
install path>\DesignExamples\Tutorials\SOPCBuilder\AvalonFIFO.
folder.
The Quartus II software automatically specifies a top-level design entity
that has the same name as the project. This tutorial assumes that the names
are the same.
in the
“Avalon-MM Interface Blocks Design
Preliminary
“Instantiating the Design in SOPC Builder” on
Example”.
DSP Builder Standard Blockset User Guide
7–19