IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 184

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

13–8
VHDL Entity Names Change if a Model is Modified
Algebraic Loop Causes Simulation to Fail
DSP Builder Standard Blockset User Guide
f
This problem is caused by corrupted Librarian IP cache and can be resolved by
deleting the IP cache directory which is normally located at:
The Signal Compiler VHDL files have a random number suffix appended to the file if
you modify the model.
For example, if you change the pipeline delay on a Delay block, the corresponding
VHDL file: alt_dspbuilder_delay_<randomnumber> changes, while the VHDL file
name for the rest of the blocks in the model remain the same.
Solve this problem with a regular expression in the project assignments
Quartus II Assignments to Block Entity Names” on page
HDL import and IP Toolbench-based MegaCore function blocks provide an interface
for changing the direct feedthrough settings of their inputs.
Algebraic loops are loops entirely consisting of blocks having some inputs that are
direct feedthrough, that is, inputs that have a purely combinational path to at least
one output of the block.
For more information about algebraic loops, refer to the MATLAB Help.
The feature to automatically infer the correct direct feedthrough values is disabled by
default for HDL Import (and DSP Builder treats all inputs as direct feedthrough).
Enable it by typing the following command in the MATLAB command window:
The direct feedthrough settings for the HDL Import block update after a successful
compile of the HDL when this parameter is on.
A more direct method of changing the direct feedthrough settings is to modify the
InDelayed parameter on HDL Import or MegaCore function blocks, with the following
command:
For example, if the block is named My_HDL:
A valid value of this parameter is a series of digits, one for each of the inputs on the
block (from top to bottom), with a 0 indicating direct feedthrough, and a 1 indicating
that all paths to outputs from this input are registered.
C:\Documents and Settings\<user>\.altera.quartus\ip_cache
set_param(<HDL Import block name>, 'use_dynamic_feedthrough_data', 'on')
1
set_param(<block name>, 'inDelayed', <feedthrough setting>)
set_param(<My_HDL>, 'inDelayed', '1 0 0 1')
1
This feature may not generate correct settings when importing low-level
LPM-based HDL.
Specifying a value of 1 for an input, when it is in fact direct feedthrough,
causes Simulink to treat combinational paths as registered, and results in
incorrect simulation results.
Preliminary
3–27).
© June 2010 Altera Corporation
Troubleshooting Issues
(“Making
Chapter :