IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 275

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
If Statement
Table 4–21. If Statement Block Parameters
Table 4–22. If Statement Block I/O Formats
© June 2010 Altera Corporation
Number of Inputs
IF Expression
Data Bus Type
[number of bits].[]
[].[number of bits]
Use ELSE Output Port On or Off
Use ELSE IF Input
Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
….
Ii
…
In
O1
O2
[L].[R]
[LI].[RI]
[L1].[R1]
[LN].[RN]
Name
[1]
[1]
Table
Simulink (2),
is an input port. O1
4–22:
Table 4–21
Table 4–22
(3)
2–10
User Defined
Signed Integer,
Signed Fractional,
Unsigned Integer
Single Bit, Inferred
>= 0
(Parameterizable)
>= 0
(Parameterizable)
On or Off
[L].[R]
Value
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
…
Ii: in STD_LOGIC_VECTOR({LI + RI - 1} DOWNTO 0)
….
In: in STD_LOGIC_VECTOR({LN + RN - 1} DOWNTO 0)
O1: out STD_LOGIC
O2: out STD_LOGIC
shows the If Statement block parameters.
shows the If Statement block I/O formats.
(Note 1)
Specify the number of inputs to the If Statement.
Specify the if condition with any of the following operators: &, |, $, =, ~, >, <,
or (), the variables a, b, c, d, e, f, g, h, i, or j, and the single digit numerals 0,
1.
Specify the bus number format that you want to use. The selected type must
be capable of expressing 0 and 1 exactly.
Specify the number of bits to the left of the binary point.
Specify the number of bits to the right of the binary point for the gain. This
option is zero (0) unless Signed Fractional is selected.
This option turns on the false output, which implements an ELSE
condition and goes high if the condition evaluated by the If Statement
block is false.
This option turns on the else input, which implements an ELSE IF input,
when you want to cascade multiple IF Statement blocks together or as
an enable for the block.
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Implicit
Explicit
4–13
(4)