IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 218

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2–10
Table 2–17. Divider Block Parameters (Part 2 of 2)
Table 2–18. Divider Block I/O Formats
Figure 2–5. Divider Block Example
DSP
DSP Builder Standard Blockset Libraries
[].[number of bits]
Number of Pipeline
Stages
Use Enable Port
Use Asynchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
O2
[L].[R]
Name
[L].[R]
[L].[R]
[1]
[1]
[L].[R]
[L].[R]
Table
Simulink (2),
is an input port. O1
2–18:
>= 0
(Parameterizable)
0 to number of bits
(Parameterizable)
On or Off
On or Off
(3)
Table 2–18
Figure 2–5
The DSP block consists of one to four multipliers feeding a parallel adder. It is
equivalent to the
chaining) that are available only on Stratix IV and Stratix III DSP blocks.
The DSP block accepts one to four pairs of multiplier inputs a and b. The operands in
each pair are multiplied together. The second and fourth multiplier outputs can
optionally be added or subtracted from the total.
[L].[R]
Value
I1: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
O2: out STD_LOGIC_VECTOR({L + R - 1} DOWNTO 0)
is an output port.
shows the Divider block I/O formats.
shows an example with the Divider block.
(Note 1)
Specify the number of bits to the right of the binary point. This option applies
only to signed fractional formats.
When non-zero, adds pipeline stages to increase the data throughput. The clock
enable and asynchronous clear ports are available only if the block is registered
(that is, if the number of pipeline stages is greater than or equal to 1).
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Multiply Add
Preliminary
VHDL
block but exposes extra features (including
Description
© June 2010 Altera Corporation
Chapter 2: Arithmetic Library
Explicit
Explicit
Explicit
Explicit
Type
(4)
DSP